[llvm-branch-commits] [llvm] 4ab704d - [AMDGPU][MC] Add tfe disassembler support MIMG opcodes
Petar Avramovic via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jan 20 01:41:59 PST 2021
Author: Petar Avramovic
Date: 2021-01-20T10:37:09+01:00
New Revision: 4ab704d62820396af5bd4a4322a5cbc2700a7ec3
URL: https://github.com/llvm/llvm-project/commit/4ab704d62820396af5bd4a4322a5cbc2700a7ec3
DIFF: https://github.com/llvm/llvm-project/commit/4ab704d62820396af5bd4a4322a5cbc2700a7ec3.diff
LOG: [AMDGPU][MC] Add tfe disassembler support MIMG opcodes
With tfe on there can be a vgpr write to vdata+1.
Add tablegen support for 5 register vdata store.
This is required for 4 register vdata store with tfe.
Differential Revision: https://reviews.llvm.org/D94960
Added:
Modified:
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/MIMGInstructions.td
llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 08b340c8fd66..4a4aad02938a 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -545,9 +545,8 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
DstSize = (DstSize + 1) / 2;
}
- // FIXME: Add tfe support
if (MI.getOperand(TFEIdx).getImm())
- return MCDisassembler::Success;
+ DstSize += 1;
if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
return MCDisassembler::Success;
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 7baa6823d16a..54c8cdf196ac 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -413,6 +413,8 @@ multiclass MIMG_Store <bits<8> op, string asm, bit has_d16, bit mip = 0> {
defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>;
let VDataDwords = 4 in
defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>;
+ let VDataDwords = 5 in
+ defm _V5 : MIMG_Store_Addr_Helper <op, asm, VReg_160, 0>;
}
}
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
index 1e688c94d793..4b9c899003e4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
@@ -43,6 +43,54 @@
# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00]
0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00
+# GFX10: image_load v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x03,0x00,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x03,0x00,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_load v[16:18], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x07,0x00,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x07,0x00,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_load v[16:19], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x00,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x0f,0x00,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x01,0x01,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x01,0x01,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_load v[16:18], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x03,0x01,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x03,0x01,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_load v[16:19], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x07,0x01,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x07,0x01,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_load v[16:20], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x0f,0x01,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x0f,0x01,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_load v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_load v16, v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x03,0x00,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x03,0x00,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x07,0x00,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x07,0x00,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x0f,0x00,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x0f,0x00,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x01,0x01,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x01,0x01,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_load v[16:17], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x03,0x01,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x03,0x01,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_load v[16:18], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x07,0x01,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x07,0x01,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_load v[16:18], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x0f,0x01,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x0f,0x01,0xf0,0x08,0x10,0x18,0x80
+
# GFX10: image_store v16, v[8:9], s[96:103] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x08,0x14,0x20,0xf0,0x08,0x10,0x18,0x00]
0x08,0x14,0x20,0xf0,0x08,0x10,0x18,0x00
@@ -64,6 +112,54 @@
# GFX10: image_store_mip_pck v[16:19], v[8:11], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x10,0x1f,0x2c,0xf0,0x08,0x10,0x18,0x00]
0x10,0x1f,0x2c,0xf0,0x08,0x10,0x18,0x00
+# GFX10: image_store v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x20,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x01,0x20,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x03,0x20,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x03,0x20,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_store v[16:18], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x07,0x20,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x07,0x20,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_store v[16:19], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x20,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x0f,0x20,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x01,0x21,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x01,0x21,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_store v[16:18], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x03,0x21,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x03,0x21,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_store v[16:19], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x07,0x21,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x07,0x21,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_store v[16:20], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x08,0x0f,0x21,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x0f,0x21,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_store v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x01,0x20,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x01,0x20,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_store v16, v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x03,0x20,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x03,0x20,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x07,0x20,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x07,0x20,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D d16 ; encoding: [0x08,0x0f,0x20,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x0f,0x20,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x01,0x21,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x01,0x21,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_store v[16:17], v[8:9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x03,0x21,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x03,0x21,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_store v[16:18], v[8:9], s[96:103] dmask:0x7 dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x07,0x21,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x07,0x21,0xf0,0x08,0x10,0x18,0x80
+
+# GFX10: image_store v[16:18], v[8:9], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D tfe d16 ; encoding: [0x08,0x0f,0x21,0xf0,0x08,0x10,0x18,0x80]
+0x08,0x0f,0x21,0xf0,0x08,0x10,0x18,0x80
+
# GFX10: image_get_resinfo v[16:19], v8, s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm ; encoding: [0x28,0x1f,0x38,0xf0,0x08,0x10,0x18,0x00]
0x28,0x1f,0x38,0xf0,0x08,0x10,0x18,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
index 55543719a8ae..1e7d9a6afff5 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
@@ -3429,7 +3429,7 @@
# CHECK: image_load v5, v1, s[8:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00]
0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00
-# CHECK: image_load v5, v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
+# CHECK: image_load v[5:6], v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00
# CHECK: image_load v5, v1, s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x02,0xf0,0x01,0x05,0x02,0x00]
@@ -3510,7 +3510,7 @@
# CHECK: image_load_mip v5, v1, s[8:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00]
0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00
-# CHECK: image_load_mip v5, v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
+# CHECK: image_load_mip v[5:6], v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00
# CHECK: image_load_mip v5, v1, s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x06,0xf0,0x01,0x05,0x02,0x00]
@@ -3747,7 +3747,7 @@
# CHECK: image_get_resinfo v5, v1, s[8:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00]
0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00
-# CHECK: image_get_resinfo v5, v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
+# CHECK: image_get_resinfo v[5:6], v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00
# CHECK: image_get_resinfo v5, v1, s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x3a,0xf0,0x01,0x05,0x02,0x00]
@@ -4263,7 +4263,7 @@
# CHECK: image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x80,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x80,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x81,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x81,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x81,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x82,0xf0,0x01,0x05,0x62,0x00]
@@ -4353,7 +4353,7 @@
# CHECK: image_sample_cl v5, v1, s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_cl v5, v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_cl v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_cl v5, v1, s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x86,0xf0,0x01,0x05,0x62,0x00]
@@ -4443,7 +4443,7 @@
# CHECK: image_sample_l v5, v1, s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_l v5, v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_l v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_l v5, v1, s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x92,0xf0,0x01,0x05,0x62,0x00]
@@ -4533,7 +4533,7 @@
# CHECK: image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x96,0xf0,0x01,0x05,0x62,0x00]
@@ -4623,7 +4623,7 @@
# CHECK: image_sample_b_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x98,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x98,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_b_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x99,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_b_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x99,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x99,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_b_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x9a,0xf0,0x01,0x05,0x62,0x00]
@@ -4713,7 +4713,7 @@
# CHECK: image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x9c,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x9c,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x9d,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x9d,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x9d,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x9e,0xf0,0x01,0x05,0x62,0x00]
@@ -4803,7 +4803,7 @@
# CHECK: image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xa2,0xf0,0x01,0x05,0x62,0x00]
@@ -4893,7 +4893,7 @@
# CHECK: image_sample_c_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xa4,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xa4,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_c_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xa5,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_c_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xa5,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xa5,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_c_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xa6,0xf0,0x01,0x05,0x62,0x00]
@@ -4983,7 +4983,7 @@
# CHECK: image_sample_c_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xb0,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xb0,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_c_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xb1,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_c_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xb1,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xb1,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_c_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xb2,0xf0,0x01,0x05,0x62,0x00]
@@ -5073,7 +5073,7 @@
# CHECK: image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xb4,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xb4,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xb5,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xb5,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xb5,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xb6,0xf0,0x01,0x05,0x62,0x00]
@@ -5163,7 +5163,7 @@
# CHECK: image_sample_c_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xb8,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xb8,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_c_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xb9,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_c_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xb9,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xb9,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_c_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xba,0xf0,0x01,0x05,0x62,0x00]
@@ -5253,7 +5253,7 @@
# CHECK: image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xbe,0xf0,0x01,0x05,0x62,0x00]
@@ -6642,7 +6642,7 @@
# CHECK: image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x80,0xf3,0x01,0x05,0x62,0x00]
0x00,0x01,0x80,0xf3,0x01,0x05,0x62,0x00
-# CHECK: image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x81,0xf1,0x01,0x05,0x62,0x00]
+# CHECK: image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x81,0xf1,0x01,0x05,0x62,0x00]
0x00,0x01,0x81,0xf1,0x01,0x05,0x62,0x00
# CHECK: image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x82,0xf1,0x01,0x05,0x62,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
index c7c153039a76..8af77e0d246b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
@@ -5292,7 +5292,7 @@
# CHECK: image_load v5, v1, s[8:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00]
0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00
-# CHECK: image_load v5, v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
+# CHECK: image_load v[5:6], v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00
# CHECK: image_load v5, v1, s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x02,0xf0,0x01,0x05,0x02,0x00]
@@ -5304,7 +5304,7 @@
# CHECK: image_load v5, v1, s[8:15] dmask:0x1 d16 ; encoding: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x80]
0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x80
-# CHECK: image_load v0, v5, s[0:7] dmask:0xf unorm tfe ; encoding: [0x00,0x1f,0x01,0xf0,0x05,0x00,0x00,0x00]
+# CHECK: image_load v[0:4], v5, s[0:7] dmask:0xf unorm tfe ; encoding: [0x00,0x1f,0x01,0xf0,0x05,0x00,0x00,0x00]
0x00,0x1f,0x01,0xf0,0x05,0x00,0x00,0x00
# CHECK: image_load_mip v5, v1, s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
@@ -5373,7 +5373,7 @@
# CHECK: image_load_mip v5, v1, s[8:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00]
0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00
-# CHECK: image_load_mip v5, v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
+# CHECK: image_load_mip v[5:6], v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00
# CHECK: image_load_mip v5, v1, s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x06,0xf0,0x01,0x05,0x02,0x00]
@@ -5604,7 +5604,7 @@
# CHECK: image_get_resinfo v5, v1, s[8:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00]
0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00
-# CHECK: image_get_resinfo v5, v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
+# CHECK: image_get_resinfo v[5:6], v1, s[8:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00
# CHECK: image_get_resinfo v5, v1, s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x3a,0xf0,0x01,0x05,0x02,0x00]
@@ -6075,7 +6075,7 @@
# CHECK: image_sample_cl v5, v1, s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_cl v5, v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_cl v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_cl v5, v1, s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x86,0xf0,0x01,0x05,0x62,0x00]
@@ -6159,7 +6159,7 @@
# CHECK: image_sample_l v5, v1, s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_l v5, v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_l v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_l v5, v1, s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x92,0xf0,0x01,0x05,0x62,0x00]
@@ -6243,7 +6243,7 @@
# CHECK: image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x96,0xf0,0x01,0x05,0x62,0x00]
@@ -6327,7 +6327,7 @@
# CHECK: image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xa2,0xf0,0x01,0x05,0x62,0x00]
@@ -6411,7 +6411,7 @@
# CHECK: image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xbe,0xf0,0x01,0x05,0x62,0x00]
@@ -6495,7 +6495,7 @@
# CHECK: image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xc0,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xc0,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xc1,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xc1,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xc1,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xc2,0xf0,0x01,0x05,0x62,0x00]
@@ -6579,7 +6579,7 @@
# CHECK: image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc ; encoding: [0x00,0x01,0xdc,0xf2,0x01,0x05,0x62,0x00]
0x00,0x01,0xdc,0xf2,0x01,0x05,0x62,0x00
-# CHECK: image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xdd,0xf0,0x01,0x05,0x62,0x00]
+# CHECK: image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe ; encoding: [0x00,0x01,0xdd,0xf0,0x01,0x05,0x62,0x00]
0x00,0x01,0xdd,0xf0,0x01,0x05,0x62,0x00
# CHECK: image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0xde,0xf0,0x01,0x05,0x62,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt
index dba785101e57..1566779a28fa 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt
@@ -31,8 +31,7 @@
# Test all modifiers
# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-# FIXME: This test is incorrect because tfe shall increase data size by 1.
-# VI: image_load v5, v1, s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
+# VI: image_load v[5:6], v1, s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80
# Test dmask == 0
@@ -77,6 +76,29 @@
# GFX81: image_store v[0:1], v4, s[8:15] dmask:0xf d16 ; encoding: [0x00,0x0f,0x20,0xf0,0x04,0x00,0x02,0x80]
0x00,0x0f,0x20,0xf0,0x04,0x00,0x02,0x80
+# GFX80: image_load v[0:2], v4, s[8:15] dmask:0x3 tfe d16 ; encoding: [0x00,0x03,0x01,0xf0,0x04,0x00,0x02,0x80]
+# GFX81: image_load v[0:1], v4, s[8:15] dmask:0x3 tfe d16 ; encoding: [0x00,0x03,0x01,0xf0,0x04,0x00,0x02,0x80]
+0x00,0x03,0x01,0xf0,0x04,0x00,0x02,0x80
+
+# GFX80: image_load v[0:3], v4, s[8:15] dmask:0x7 tfe d16 ; encoding: [0x00,0x07,0x01,0xf0,0x04,0x00,0x02,0x80]
+# GFX81: image_load v[0:2], v4, s[8:15] dmask:0x7 tfe d16 ; encoding: [0x00,0x07,0x01,0xf0,0x04,0x00,0x02,0x80]
+0x00,0x07,0x01,0xf0,0x04,0x00,0x02,0x80
+
+# GFX80: image_load v[0:4], v4, s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x04,0x00,0x02,0x80]
+# GFX81: image_load v[0:2], v4, s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x04,0x00,0x02,0x80]
+0x00,0x0f,0x01,0xf0,0x04,0x00,0x02,0x80
+
+# GFX80: image_store v[0:2], v4, s[8:15] dmask:0x3 tfe d16 ; encoding: [0x00,0x03,0x21,0xf0,0x04,0x00,0x02,0x80]
+# GFX81: image_store v[0:1], v4, s[8:15] dmask:0x3 tfe d16 ; encoding: [0x00,0x03,0x21,0xf0,0x04,0x00,0x02,0x80]
+0x00,0x03,0x21,0xf0,0x04,0x00,0x02,0x80
+
+# GFX80: image_store v[0:3], v4, s[8:15] dmask:0x7 tfe d16 ; encoding: [0x00,0x07,0x21,0xf0,0x04,0x00,0x02,0x80]
+# GFX81: image_store v[0:2], v4, s[8:15] dmask:0x7 tfe d16 ; encoding: [0x00,0x07,0x21,0xf0,0x04,0x00,0x02,0x80]
+0x00,0x07,0x21,0xf0,0x04,0x00,0x02,0x80
+
+# GFX80: image_store v[0:4], v4, s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x21,0xf0,0x04,0x00,0x02,0x80]
+# GFX81: image_store v[0:2], v4, s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x21,0xf0,0x04,0x00,0x02,0x80]
+0x00,0x0f,0x21,0xf0,0x04,0x00,0x02,0x80
#===------------------------------------------------------------------------===#
# Image load/store: PCK variants
#===------------------------------------------------------------------------===#
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