[llvm-branch-commits] [llvm] 9cf511a - [RISCV] Add intrinsics for vector AMO operations
ShihPo Hung via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Jan 18 23:19:09 PST 2021
Author: ShihPo Hung
Date: 2021-01-18T23:11:10-08:00
New Revision: 9cf511aa08ae2a5b94e9cefe3fc60cc33358519b
URL: https://github.com/llvm/llvm-project/commit/9cf511aa08ae2a5b94e9cefe3fc60cc33358519b
DIFF: https://github.com/llvm/llvm-project/commit/9cf511aa08ae2a5b94e9cefe3fc60cc33358519b.diff
LOG: [RISCV] Add intrinsics for vector AMO operations
Add vamoswap, vamoadd, vamoxor, vamoand, vamoor,
vamomin, vamomax, vamominu, vamomaxu intrinsics.
Reviewed By: craig.topper, khchen
Differential Revision: https://reviews.llvm.org/D94589
Added:
llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index e45be2b72796..bcf0169f7f31 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -469,6 +469,20 @@ let TargetPrefix = "riscv" in {
[LLVMMatchType<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic;
+ // For atomic operations without mask
+ // Input: (base, index, value, vl)
+ class RISCVAMONoMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty, LLVMMatchType<0>,
+ llvm_anyint_ty],
+ [NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;
+ // For atomic operations with mask
+ // Input: (base, index, value, mask, vl)
+ class RISCVAMOMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty, LLVMMatchType<0>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+ [NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;
multiclass RISCVUSLoad {
def "int_riscv_" # NAME : RISCVUSLoad;
@@ -568,6 +582,10 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" #NAME :RISCVConversionNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVConversionMask;
}
+ multiclass RISCVAMO {
+ def "int_riscv_" # NAME : RISCVAMONoMask;
+ def "int_riscv_" # NAME # "_mask" : RISCVAMOMask;
+ }
defm vle : RISCVUSLoad;
defm vleff : RISCVUSLoad;
@@ -578,6 +596,16 @@ let TargetPrefix = "riscv" in {
defm vsxe: RISCVIStore;
defm vsuxe: RISCVIStore;
+ defm vamoswap : RISCVAMO;
+ defm vamoadd : RISCVAMO;
+ defm vamoxor : RISCVAMO;
+ defm vamoand : RISCVAMO;
+ defm vamoor : RISCVAMO;
+ defm vamomin : RISCVAMO;
+ defm vamomax : RISCVAMO;
+ defm vamominu : RISCVAMO;
+ defm vamomaxu : RISCVAMO;
+
defm vadd : RISCVBinaryAAX;
defm vsub : RISCVBinaryAAX;
defm vrsub : RISCVBinaryAAX;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 1e52fef2441b..1406c8645f73 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -73,10 +73,38 @@ def MxList {
list<LMULInfo> m = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
}
+class MxSet<int eew> {
+ list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
+}
+
class shift_amount<int num> {
int val = !if(!eq(num, 1), 0, !add(1, shift_amount<!srl(num, 1)>.val));
}
+class octuple_from_str<string MX> {
+ int ret = !cond(!eq(MX, "MF8") : 1,
+ !eq(MX, "MF4") : 2,
+ !eq(MX, "MF2") : 4,
+ !eq(MX, "M1") : 8,
+ !eq(MX, "M2") : 16,
+ !eq(MX, "M4") : 32,
+ !eq(MX, "M8") : 64);
+}
+
+class octuple_to_str<int octuple> {
+ string ret = !if(!eq(octuple, 1), "MF8",
+ !if(!eq(octuple, 2), "MF4",
+ !if(!eq(octuple, 4), "MF2",
+ !if(!eq(octuple, 8), "M1",
+ !if(!eq(octuple, 16), "M2",
+ !if(!eq(octuple, 32), "M4",
+ !if(!eq(octuple, 64), "M8",
+ "NoDef")))))));
+}
+
// Output pattern for X0 used to represent VLMAX in the pseudo instructions.
def VLMax : OutPatFrag<(ops), (XLenVT X0)>;
@@ -826,6 +854,74 @@ class VPseudoTernaryNoMask<VReg RetClass,
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
+class VPseudoAMOWDNoMask<VReg RetClass,
+ VReg Op1Class> :
+ Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
+ (ins GPR:$rs1,
+ Op1Class:$vs2,
+ GetVRegNoV0<RetClass>.R:$vd,
+ GPR:$vl, ixlenimm:$sew), []>,
+ RISCVVPseudo {
+ let mayLoad = 1;
+ let mayStore = 1;
+ let hasSideEffects = 1;
+ let usesCustomInserter = 1;
+ let Constraints = "$vd_wd = $vd";
+ let Uses = [VL, VTYPE];
+ let HasVLOp = 1;
+ let HasSEWOp = 1;
+ let HasDummyMask = 1;
+ let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+class VPseudoAMOWDMask<VReg RetClass,
+ VReg Op1Class> :
+ Pseudo<(outs GetVRegNoV0<RetClass>.R:$vd_wd),
+ (ins GPR:$rs1,
+ Op1Class:$vs2,
+ GetVRegNoV0<RetClass>.R:$vd,
+ VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+ RISCVVPseudo {
+ let mayLoad = 1;
+ let mayStore = 1;
+ let hasSideEffects = 1;
+ let usesCustomInserter = 1;
+ let Constraints = "$vd_wd = $vd";
+ let Uses = [VL, VTYPE];
+ let HasVLOp = 1;
+ let HasSEWOp = 1;
+ let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+multiclass VPseudoAMOEI<int eew> {
+ // Standard scalar AMO supports 32, 64, and 128 Mem data bits,
+ // and in the base vector "V" extension, only SEW up to ELEN = max(XLEN, FLEN)
+ // are required to be supported.
+ // therefore only [32, 64] is allowed here.
+ foreach sew = [32, 64] in {
+ foreach lmul = MxSet<sew>.m in {
+ defvar octuple_lmul = octuple_from_str<lmul.MX>.ret;
+ // Calculate emul = eew * lmul / sew
+ defvar octuple_emul = !srl(!mul(eew, octuple_lmul), shift_amount<sew>.val);
+ if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
+ defvar emulMX = octuple_to_str<octuple_emul>.ret;
+ defvar lmulMX = octuple_to_str<octuple_lmul>.ret;
+ defvar emul= !cast<LMULInfo>("V_" # emulMX);
+ defvar lmul = !cast<LMULInfo>("V_" # lmulMX);
+ let VLMul = lmul.value in {
+ def "_WD_" # lmulMX # "_" # emulMX : VPseudoAMOWDNoMask<lmul.vrclass, emul.vrclass>;
+ def "_WD_" # lmulMX # "_" # emulMX # "_MASK" : VPseudoAMOWDMask<lmul.vrclass, emul.vrclass>;
+ }
+ }
+ }
+ }
+}
+
+multiclass VPseudoAMO {
+ foreach eew = EEWList in
+ defm "EI" # eew : VPseudoAMOEI<eew>;
+}
+
multiclass VPseudoUSLoad {
foreach lmul = MxList.m in {
defvar LInfo = lmul.MX;
@@ -1508,6 +1604,42 @@ class VPatTernaryMask<string intrinsic,
(mask_type V0),
(NoX0 GPR:$vl), sew)>;
+class VPatAMOWDNoMask<string intrinsic_name,
+ string inst,
+ ValueType result_type,
+ ValueType op1_type,
+ int sew,
+ LMULInfo vlmul,
+ LMULInfo emul,
+ VReg op1_reg_class> :
+ Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
+ GPR:$rs1,
+ (op1_type op1_reg_class:$vs2),
+ (result_type vlmul.vrclass:$vd),
+ (XLenVT GPR:$vl))),
+ (!cast<Instruction>(inst # "_WD_" # vlmul.MX # "_" # emul.MX)
+ $rs1, $vs2, $vd,
+ (NoX0 GPR:$vl), sew)>;
+
+class VPatAMOWDMask<string intrinsic_name,
+ string inst,
+ ValueType result_type,
+ ValueType op1_type,
+ ValueType mask_type,
+ int sew,
+ LMULInfo vlmul,
+ LMULInfo emul,
+ VReg op1_reg_class> :
+ Pat<(result_type (!cast<Intrinsic>(intrinsic_name # "_mask")
+ GPR:$rs1,
+ (op1_type op1_reg_class:$vs2),
+ (result_type vlmul.vrclass:$vd),
+ (mask_type V0),
+ (XLenVT GPR:$vl))),
+ (!cast<Instruction>(inst # "_WD_" # vlmul.MX # "_" # emul.MX # "_MASK")
+ $rs1, $vs2, $vd,
+ (mask_type V0), (NoX0 GPR:$vl), sew)>;
+
multiclass VPatUSLoad<string intrinsic,
string inst,
LLVMType type,
@@ -2383,6 +2515,44 @@ multiclass VPatConversionVF_WF <string intrinsic, string instruction> {
}
}
+multiclass VPatAMOWD<string intrinsic,
+ string inst,
+ ValueType result_type,
+ ValueType offset_type,
+ ValueType mask_type,
+ int sew,
+ LMULInfo vlmul,
+ LMULInfo emul,
+ VReg op1_reg_class>
+{
+ def : VPatAMOWDNoMask<intrinsic, inst, result_type, offset_type,
+ sew, vlmul, emul, op1_reg_class>;
+ def : VPatAMOWDMask<intrinsic, inst, result_type, offset_type,
+ mask_type, sew, vlmul, emul, op1_reg_class>;
+}
+
+multiclass VPatAMOV_WD<string intrinsic,
+ string inst,
+ list<VTypeInfo> vtilist> {
+ foreach eew = EEWList in {
+ foreach vti = vtilist in {
+ if !or(!eq(vti.SEW, 32), !eq(vti.SEW, 64)) then {
+ defvar octuple_lmul = octuple_from_str<vti.LMul.MX>.ret;
+ // Calculate emul = eew * lmul / sew
+ defvar octuple_emul = !srl(!mul(eew, octuple_lmul), shift_amount<vti.SEW>.val);
+ if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
+ defvar emulMX = octuple_to_str<octuple_emul>.ret;
+ defvar offsetVti = !cast<VTypeInfo>("VI" # eew # emulMX);
+ defvar inst_ei = inst # "EI" # eew;
+ defm : VPatAMOWD<intrinsic, inst_ei,
+ vti.Vector, offsetVti.Vector,
+ vti.Mask, vti.SEW, vti.LMul, offsetVti.LMul, offsetVti.RegClass>;
+ }
+ }
+ }
+ }
+}
+
//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//
@@ -2459,6 +2629,19 @@ foreach eew = EEWList in {
defm PseudoVLE # eew # FF : VPseudoUSLoad;
}
+//===----------------------------------------------------------------------===//
+// 8. Vector AMO Operations
+//===----------------------------------------------------------------------===//
+defm PseudoVAMOSWAP : VPseudoAMO;
+defm PseudoVAMOADD : VPseudoAMO;
+defm PseudoVAMOXOR : VPseudoAMO;
+defm PseudoVAMOAND : VPseudoAMO;
+defm PseudoVAMOOR : VPseudoAMO;
+defm PseudoVAMOMIN : VPseudoAMO;
+defm PseudoVAMOMAX : VPseudoAMO;
+defm PseudoVAMOMINU : VPseudoAMO;
+defm PseudoVAMOMAXU : VPseudoAMO;
+
//===----------------------------------------------------------------------===//
// 12. Vector Integer Arithmetic Instructions
//===----------------------------------------------------------------------===//
@@ -2983,13 +3166,7 @@ foreach vti = AllVectors in
foreach vti = AllVectors in
foreach eew = EEWList in {
defvar vlmul = vti.LMul;
- defvar octuple_lmul = !cond(!eq(vti.LMul.MX, "MF8") : 1,
- !eq(vti.LMul.MX, "MF4") : 2,
- !eq(vti.LMul.MX, "MF2") : 4,
- !eq(vti.LMul.MX, "M1") : 8,
- !eq(vti.LMul.MX, "M2") : 16,
- !eq(vti.LMul.MX, "M4") : 32,
- !eq(vti.LMul.MX, "M8") : 64);
+ defvar octuple_lmul = octuple_from_str<vti.LMul.MX>.ret;
defvar log_sew = shift_amount<vti.SEW>.val;
// The data vector register group has EEW=SEW, EMUL=LMUL, while the offset
// vector register group has EEW encoding in the instruction and EMUL=(EEW/SEW)*LMUL.
@@ -2998,13 +3175,7 @@ foreach eew = EEWList in {
// legal octuple elmul should be more than 0 and less than equal 64
if !gt(octuple_elmul, 0) then {
if !le(octuple_elmul, 64) then {
- defvar log_elmul = shift_amount<octuple_elmul>.val;
- // 0, 1, 2 -> V_MF8 ~ V_MF2
- // 3, 4, 5, 6 -> V_M1 ~ V_M8
- defvar elmul_str = !if(!eq(log_elmul, 0), "MF8",
- !if(!eq(log_elmul, 1), "MF4",
- !if(!eq(log_elmul, 2), "MF2",
- "M" # !cast<string>(!shl(1, !add(log_elmul, -3))))));
+ defvar elmul_str = octuple_to_str<octuple_elmul>.ret;
defvar elmul =!cast<LMULInfo>("V_" # elmul_str);
defvar idx_vti = !cast<VTypeInfo>("VI" # eew # elmul_str);
@@ -3023,12 +3194,32 @@ foreach eew = EEWList in {
}
}
}
+} // Predicates = [HasStdExtV]
+//===----------------------------------------------------------------------===//
+// 8. Vector AMO Operations
+//===----------------------------------------------------------------------===//
+let Predicates = [HasStdExtZvamo] in {
+ defm "" : VPatAMOV_WD<"int_riscv_vamoswap", "PseudoVAMOSWAP", AllIntegerVectors>;
+ defm "" : VPatAMOV_WD<"int_riscv_vamoadd", "PseudoVAMOADD", AllIntegerVectors>;
+ defm "" : VPatAMOV_WD<"int_riscv_vamoxor", "PseudoVAMOXOR", AllIntegerVectors>;
+ defm "" : VPatAMOV_WD<"int_riscv_vamoand", "PseudoVAMOAND", AllIntegerVectors>;
+ defm "" : VPatAMOV_WD<"int_riscv_vamoor", "PseudoVAMOOR", AllIntegerVectors>;
+ defm "" : VPatAMOV_WD<"int_riscv_vamomin", "PseudoVAMOMIN", AllIntegerVectors>;
+ defm "" : VPatAMOV_WD<"int_riscv_vamomax", "PseudoVAMOMAX", AllIntegerVectors>;
+ defm "" : VPatAMOV_WD<"int_riscv_vamominu", "PseudoVAMOMINU", AllIntegerVectors>;
+ defm "" : VPatAMOV_WD<"int_riscv_vamomaxu", "PseudoVAMOMAXU", AllIntegerVectors>;
+} // Predicates = [HasStdExtZvamo]
+
+let Predicates = [HasStdExtZvamo, HasStdExtF] in {
+ defm "" : VPatAMOV_WD<"int_riscv_vamoswap", "PseudoVAMOSWAP", AllFloatVectors>;
+} // Predicates = [HasStdExtZvamo, HasStdExtF]
//===----------------------------------------------------------------------===//
// 12. Vector Integer Arithmetic Instructions
//===----------------------------------------------------------------------===//
+let Predicates = [HasStdExtV] in {
//===----------------------------------------------------------------------===//
// 12.1. Vector Single-Width Integer Add and Subtract
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll
new file mode 100644
index 000000000000..76ec5af07a8e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll
@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll
new file mode 100644
index 000000000000..1d813f02022d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll
@@ -0,0 +1,1714 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoadd.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoadd_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoaddei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoadd.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoadd_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoaddei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoadd.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoadd_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoaddei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoadd.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoadd_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoaddei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoadd.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoadd_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoaddei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoadd.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoadd_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoaddei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoadd.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoadd_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoaddei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoadd.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoadd_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoaddei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoadd.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoadd_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoadd.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoadd_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoadd.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoadd_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoadd.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoadd_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoadd.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoadd_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoadd.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoadd_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoadd.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoadd_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoadd.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoadd_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoadd.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoadd_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoadd.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoadd_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoadd.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoadd_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoadd.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoadd_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoadd.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoadd_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoadd.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoadd_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoadd.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoadd_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoadd.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoadd_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoadd_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoadd_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoadd_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoadd_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoadd.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoadd_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoadd.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoadd_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoadd.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoadd_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoadd.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoadd_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoadd.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoadd_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoadd.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoadd_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoadd.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoadd_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoadd.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoadd_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll
new file mode 100644
index 000000000000..794defb41409
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll
@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll
new file mode 100644
index 000000000000..597ccdad3dca
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll
@@ -0,0 +1,1714 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoand.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoand_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoandei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoand.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoand.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoand_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoandei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoand.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoand.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoand_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoandei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoand.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoand.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoand_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoandei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoand.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoand.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoand_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoandei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoand.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoand.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoand_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoandei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoand.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoand.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoand_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoandei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoand.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoand.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoand_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoandei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoand.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoand.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoand_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoand.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoand.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoand_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoand.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoand.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoand_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoand.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoand.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoand_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoand.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoand.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoand_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoand.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoand.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoand_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoand.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoand.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoand_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoand.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoand.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoand_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoand.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoand.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoand_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoand.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoand.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoand_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoand.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoand.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoand_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoand.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoand.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoand_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoand.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoand.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoand_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoand.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoand.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoand_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoand.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoand.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoand_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoand.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoand.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoand_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoand.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoand_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoand.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoand_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoand.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoand_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoand.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoand_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoand.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoand_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoand.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoand.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoand_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoand.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoand.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoand_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoand.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoand.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoand_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoand.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoand.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoand_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoand.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoand.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoand_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoand.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoand.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoand_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoand.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoand.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoand_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoand.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoand.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoand_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoand.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll
new file mode 100644
index 000000000000..64cf32f0c16a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll
@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll
new file mode 100644
index 000000000000..48f06a2c6828
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll
@@ -0,0 +1,1714 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomax.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomax_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomax.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomax.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomax_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomax.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomax.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomax_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomax.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomax.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomax_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomax.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomax.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomax_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomax.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomax.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomax_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomax.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomax.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomax_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomax.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomax.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomax_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomax.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomax.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomax_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomax.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomax.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomax_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomax.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomax.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomax_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomax.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomax.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomax_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomax.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomax.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomax_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomax.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomax.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomax_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomax.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomax.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomax_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomax.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomax.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomax_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomax.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomax.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomax_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomax.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomax.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomax_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomax.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomax.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomax_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomax.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomax.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomax_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomax.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomax.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomax_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomax.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomax.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomax_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomax.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomax.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomax_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomax.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomax.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomax_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomax.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomax_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomax.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomax_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomax.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomax_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomax.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomax_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomax.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomax_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomax.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomax.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomax_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomax.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomax.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomax_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomax.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomax.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomax_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomax.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomax.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomax_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomax.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomax.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomax_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomax.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomax.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomax_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomax.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomax.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomax_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomax.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomax.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomax_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomax.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll
new file mode 100644
index 000000000000..9eb08e1af1d5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll
@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll
new file mode 100644
index 000000000000..7aa3afe7f086
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll
@@ -0,0 +1,1714 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxu.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxu_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxu.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxu.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxu_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxu.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxu.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxu_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxu.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxu.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxu_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxu.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxu.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxu_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxu.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxu.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxu_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxu.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxu.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxu_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxu.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxu.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxu_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxu.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxu.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxu_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxu.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxu.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxu_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxu.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxu.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxu_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxu.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxu.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxu_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxu.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxu.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxu_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxu.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxu.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxu_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxu.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxu.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxu_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxu.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxu.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxu_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxu.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamomaxuei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll
new file mode 100644
index 000000000000..a99baa11537c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll
@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll
new file mode 100644
index 000000000000..48ed6f32750b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll
@@ -0,0 +1,1714 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamominei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamominei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomin.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomin_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomin.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomin.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomin_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomin.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomin.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomin_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomin.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomin.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomin_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomin.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomin.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomin_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomin.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomin.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomin_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomin.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomin.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomin_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomin.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomin.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomin_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomin.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomin.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomin_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomin.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomin.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomin_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomin.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomin.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomin_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomin.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomin.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomin_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomin.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomin.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomin_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomin.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomin.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomin_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomin.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomin.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomin_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomin.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomin.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomin_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomin.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomin.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomin_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomin.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomin.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomin_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomin.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomin.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomin_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomin.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomin.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomin_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomin.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomin.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomin_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomin.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomin.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomin_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomin.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomin.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomin_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomin.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomin.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomin_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomin.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamomin_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamomin.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamomin_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamomin.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamomin_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamomin.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamomin_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamomin.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamomin_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamomin.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomin.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomin_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomin.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamomin.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamomin_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamomin.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomin.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomin_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomin.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamomin.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamomin_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamomin.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomin.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomin_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomin.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamomin.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamomin_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamomin.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomin.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomin_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomin.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamomin.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamomin_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamomin.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll
new file mode 100644
index 000000000000..cd9cb0a94563
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll
@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll
new file mode 100644
index 000000000000..dc4dd1578a9e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll
@@ -0,0 +1,1714 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominu.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominu_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominuei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamominu.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominu.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominu_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominuei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamominu.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominu.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominu_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominuei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamominu.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominu.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominu_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominuei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamominu.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominu.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominu_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominuei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamominu.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominu.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominu_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominuei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamominu.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominu.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominu_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominuei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamominu.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominu.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominu_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominuei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamominu.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominu.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominu_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamominu.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominu.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominu_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamominu.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominu.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominu_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamominu.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominu.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominu_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamominu.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominu.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominu_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamominu.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominu.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominu_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamominu.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominu.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominu_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamominu.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominu.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominu_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamominu.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominu.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominu_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamominu.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominu.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominu_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamominu.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominu.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominu_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamominu.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominu.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominu_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamominu.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominu.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominu_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamominu.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominu.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominu_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamominu.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominu.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominu_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamominu.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominu.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominu_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamominu.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamominu_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamominu.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamominu_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamominu.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamominu_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamominu.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamominu_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamominu.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamominu_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamominu.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominu.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominu_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamominu.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamominu.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamominu_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamominu.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominu.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominu_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamominu.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamominu.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamominu_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamominu.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominu.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominu_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamominu.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamominu.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamominu_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamominu.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominu.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominu_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamominu.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamominu.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamominu_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamominu.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll
new file mode 100644
index 000000000000..25601f2a7dd3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll
@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll
new file mode 100644
index 000000000000..9d0cb3baba2a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll
@@ -0,0 +1,1714 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoor.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoor_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoorei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoor.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoor.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoor_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoorei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoor.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoor.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoor_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoorei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoor.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoor.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoor_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoorei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoor.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoor.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoor_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoorei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoor.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoor.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoor_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoorei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoor.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoor.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoor_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoorei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoor.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoor.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoor_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoorei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoor.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoor.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoor_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoor.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoor.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoor_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoor.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoor.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoor_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoor.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoor.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoor_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoor.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoor.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoor_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoor.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoor.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoor_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoor.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoor.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoor_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoor.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoor.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoor_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoor.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoor.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoor_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoor.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoor.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoor_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoor.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoor.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoor_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoor.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoor.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoor_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoor.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoor.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoor_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoor.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoor.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoor_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoor.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoor.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoor_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoor.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoor.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoor_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoor.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoor_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoor.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoor_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoor.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoor_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoor.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoor_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoor.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoor_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoor.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoor.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoor_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoor.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoor.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoor_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoor.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoor.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoor_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoor.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoor.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoor_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoor.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoor.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoor_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoor.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoor.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoor_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoor.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoor.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoor_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoor.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoor.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoor_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoor.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll
new file mode 100644
index 000000000000..61465a6342b3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll
@@ -0,0 +1,2054 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i32(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x float>,
+ i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_v_nxv1f32_nxv1i32(<vscale x 1 x float> *%0, <vscale x 1 x i32> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i32(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x float> %2,
+ i32 %3)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i32(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x float>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_mask_v_nxv1f32_nxv1i32(<vscale x 1 x float> *%0, <vscale x 1 x i32> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i32(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x float> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i32(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x float>,
+ i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_v_nxv2f32_nxv2i32(<vscale x 2 x float> *%0, <vscale x 2 x i32> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i32(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x float> %2,
+ i32 %3)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i32(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x float>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_mask_v_nxv2f32_nxv2i32(<vscale x 2 x float> *%0, <vscale x 2 x i32> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i32(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x float> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i32(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x float>,
+ i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_v_nxv4f32_nxv4i32(<vscale x 4 x float> *%0, <vscale x 4 x i32> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i32(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x float> %2,
+ i32 %3)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i32(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x float>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_mask_v_nxv4f32_nxv4i32(<vscale x 4 x float> *%0, <vscale x 4 x i32> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i32(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x float> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i32(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x float>,
+ i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_v_nxv8f32_nxv8i32(<vscale x 8 x float> *%0, <vscale x 8 x i32> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i32(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x float> %2,
+ i32 %3)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i32(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x float>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_mask_v_nxv8f32_nxv8i32(<vscale x 8 x float> *%0, <vscale x 8 x i32> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i32(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x float> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i32(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x float>,
+ i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_v_nxv16f32_nxv16i32(<vscale x 16 x float> *%0, <vscale x 16 x i32> %1, <vscale x 16 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i32(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x float> %2,
+ i32 %3)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i32(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x float>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i32(<vscale x 16 x float> *%0, <vscale x 16 x i32> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i32(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x float> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i32(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x double>,
+ i32);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_v_nxv1f64_nxv1i32(<vscale x 1 x double> *%0, <vscale x 1 x i32> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i32(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x double> %2,
+ i32 %3)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i32(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x double>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_mask_v_nxv1f64_nxv1i32(<vscale x 1 x double> *%0, <vscale x 1 x i32> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i32(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x double> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i32(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x double>,
+ i32);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_v_nxv2f64_nxv2i32(<vscale x 2 x double> *%0, <vscale x 2 x i32> %1, <vscale x 2 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i32(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x double> %2,
+ i32 %3)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i32(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x double>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_mask_v_nxv2f64_nxv2i32(<vscale x 2 x double> *%0, <vscale x 2 x i32> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i32(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x double> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i32(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x double>,
+ i32);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_v_nxv4f64_nxv4i32(<vscale x 4 x double> *%0, <vscale x 4 x i32> %1, <vscale x 4 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i32(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x double> %2,
+ i32 %3)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i32(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x double>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_mask_v_nxv4f64_nxv4i32(<vscale x 4 x double> *%0, <vscale x 4 x i32> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i32(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x double> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i32(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x double>,
+ i32);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_v_nxv8f64_nxv8i32(<vscale x 8 x double> *%0, <vscale x 8 x i32> %1, <vscale x 8 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i32(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x double> %2,
+ i32 %3)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i32(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x double>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i32(<vscale x 8 x double> *%0, <vscale x 8 x i32> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i32(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x double> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i16(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x float>,
+ i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_v_nxv1f32_nxv1i16(<vscale x 1 x float> *%0, <vscale x 1 x i16> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i16(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x float> %2,
+ i32 %3)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i16(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x float>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_mask_v_nxv1f32_nxv1i16(<vscale x 1 x float> *%0, <vscale x 1 x i16> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i16(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x float> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i16(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x float>,
+ i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_v_nxv2f32_nxv2i16(<vscale x 2 x float> *%0, <vscale x 2 x i16> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i16(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x float> %2,
+ i32 %3)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i16(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x float>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_mask_v_nxv2f32_nxv2i16(<vscale x 2 x float> *%0, <vscale x 2 x i16> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i16(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x float> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i16(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x float>,
+ i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_v_nxv4f32_nxv4i16(<vscale x 4 x float> *%0, <vscale x 4 x i16> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i16(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x float> %2,
+ i32 %3)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i16(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x float>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_mask_v_nxv4f32_nxv4i16(<vscale x 4 x float> *%0, <vscale x 4 x i16> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i16(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x float> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i16(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x float>,
+ i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_v_nxv8f32_nxv8i16(<vscale x 8 x float> *%0, <vscale x 8 x i16> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i16(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x float> %2,
+ i32 %3)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i16(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x float>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_mask_v_nxv8f32_nxv8i16(<vscale x 8 x float> *%0, <vscale x 8 x i16> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i16(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x float> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i16(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x float>,
+ i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_v_nxv16f32_nxv16i16(<vscale x 16 x float> *%0, <vscale x 16 x i16> %1, <vscale x 16 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i16(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x float> %2,
+ i32 %3)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i16(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x float>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i16(<vscale x 16 x float> *%0, <vscale x 16 x i16> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i16(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x float> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i16(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x double>,
+ i32);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_v_nxv1f64_nxv1i16(<vscale x 1 x double> *%0, <vscale x 1 x i16> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i16(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x double> %2,
+ i32 %3)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i16(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x double>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_mask_v_nxv1f64_nxv1i16(<vscale x 1 x double> *%0, <vscale x 1 x i16> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i16(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x double> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i16(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x double>,
+ i32);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_v_nxv2f64_nxv2i16(<vscale x 2 x double> *%0, <vscale x 2 x i16> %1, <vscale x 2 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i16(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x double> %2,
+ i32 %3)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i16(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x double>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_mask_v_nxv2f64_nxv2i16(<vscale x 2 x double> *%0, <vscale x 2 x i16> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i16(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x double> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i16(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x double>,
+ i32);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_v_nxv4f64_nxv4i16(<vscale x 4 x double> *%0, <vscale x 4 x i16> %1, <vscale x 4 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i16(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x double> %2,
+ i32 %3)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i16(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x double>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_mask_v_nxv4f64_nxv4i16(<vscale x 4 x double> *%0, <vscale x 4 x i16> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i16(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x double> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i16(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x double>,
+ i32);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_v_nxv8f64_nxv8i16(<vscale x 8 x double> *%0, <vscale x 8 x i16> %1, <vscale x 8 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i16(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x double> %2,
+ i32 %3)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i16(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x double>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i16(<vscale x 8 x double> *%0, <vscale x 8 x i16> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i16(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x double> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i8(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x float>,
+ i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_v_nxv1f32_nxv1i8(<vscale x 1 x float> *%0, <vscale x 1 x i8> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i8(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x float> %2,
+ i32 %3)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i8(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x float>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_mask_v_nxv1f32_nxv1i8(<vscale x 1 x float> *%0, <vscale x 1 x i8> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i8(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x float> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i8(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x float>,
+ i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_v_nxv2f32_nxv2i8(<vscale x 2 x float> *%0, <vscale x 2 x i8> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i8(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x float> %2,
+ i32 %3)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i8(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x float>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_mask_v_nxv2f32_nxv2i8(<vscale x 2 x float> *%0, <vscale x 2 x i8> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i8(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x float> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i8(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x float>,
+ i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_v_nxv4f32_nxv4i8(<vscale x 4 x float> *%0, <vscale x 4 x i8> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i8(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x float> %2,
+ i32 %3)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i8(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x float>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_mask_v_nxv4f32_nxv4i8(<vscale x 4 x float> *%0, <vscale x 4 x i8> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i8(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x float> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i8(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x float>,
+ i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_v_nxv8f32_nxv8i8(<vscale x 8 x float> *%0, <vscale x 8 x i8> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i8(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x float> %2,
+ i32 %3)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i8(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x float>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_mask_v_nxv8f32_nxv8i8(<vscale x 8 x float> *%0, <vscale x 8 x i8> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i8(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x float> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i8(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x float>,
+ i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_v_nxv16f32_nxv16i8(<vscale x 16 x float> *%0, <vscale x 16 x i8> %1, <vscale x 16 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i8(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x float> %2,
+ i32 %3)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i8(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x float>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i8(<vscale x 16 x float> *%0, <vscale x 16 x i8> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i8(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x float> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i8(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x double>,
+ i32);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_v_nxv1f64_nxv1i8(<vscale x 1 x double> *%0, <vscale x 1 x i8> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i8(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x double> %2,
+ i32 %3)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i8(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x double>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_mask_v_nxv1f64_nxv1i8(<vscale x 1 x double> *%0, <vscale x 1 x i8> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i8(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x double> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i8(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x double>,
+ i32);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_v_nxv2f64_nxv2i8(<vscale x 2 x double> *%0, <vscale x 2 x i8> %1, <vscale x 2 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i8(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x double> %2,
+ i32 %3)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i8(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x double>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_mask_v_nxv2f64_nxv2i8(<vscale x 2 x double> *%0, <vscale x 2 x i8> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i8(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x double> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i8(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x double>,
+ i32);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_v_nxv4f64_nxv4i8(<vscale x 4 x double> *%0, <vscale x 4 x i8> %1, <vscale x 4 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i8(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x double> %2,
+ i32 %3)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i8(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x double>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_mask_v_nxv4f64_nxv4i8(<vscale x 4 x double> *%0, <vscale x 4 x i8> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i8(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x double> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i8(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x double>,
+ i32);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_v_nxv8f64_nxv8i8(<vscale x 8 x double> *%0, <vscale x 8 x i8> %1, <vscale x 8 x double> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i8(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x double> %2,
+ i32 %3)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i8(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x double>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i8(<vscale x 8 x double> *%0, <vscale x 8 x i8> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i8(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x double> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll
new file mode 100644
index 000000000000..752349273e40
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll
@@ -0,0 +1,3426 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswap.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswap_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoswap.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswap_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswap.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswap_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoswap.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswap_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswap.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswap_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoswap.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswap_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswap.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswap_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoswap.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswap_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i64(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x float>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_v_nxv1f32_nxv1i64(<vscale x 1 x float> *%0, <vscale x 1 x i64> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i64(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x float> %2,
+ i64 %3)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i64(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x float>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_mask_v_nxv1f32_nxv1i64(<vscale x 1 x float> *%0, <vscale x 1 x i64> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i64(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x float> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i64(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x float>,
+ i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_v_nxv2f32_nxv2i64(<vscale x 2 x float> *%0, <vscale x 2 x i64> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i64(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x float> %2,
+ i64 %3)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i64(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x float>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_mask_v_nxv2f32_nxv2i64(<vscale x 2 x float> *%0, <vscale x 2 x i64> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i64(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x float> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i64(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x float>,
+ i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_v_nxv4f32_nxv4i64(<vscale x 4 x float> *%0, <vscale x 4 x i64> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i64(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x float> %2,
+ i64 %3)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i64(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x float>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_mask_v_nxv4f32_nxv4i64(<vscale x 4 x float> *%0, <vscale x 4 x i64> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i64(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x float> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i64(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x float>,
+ i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_v_nxv8f32_nxv8i64(<vscale x 8 x float> *%0, <vscale x 8 x i64> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i64(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x float> %2,
+ i64 %3)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i64(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x float>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_mask_v_nxv8f32_nxv8i64(<vscale x 8 x float> *%0, <vscale x 8 x i64> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i64(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x float> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i64(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x double>,
+ i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_v_nxv1f64_nxv1i64(<vscale x 1 x double> *%0, <vscale x 1 x i64> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i64(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x double> %2,
+ i64 %3)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i64(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x double>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_mask_v_nxv1f64_nxv1i64(<vscale x 1 x double> *%0, <vscale x 1 x i64> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i64(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x double> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i64(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x double>,
+ i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_v_nxv2f64_nxv2i64(<vscale x 2 x double> *%0, <vscale x 2 x i64> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i64(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x double> %2,
+ i64 %3)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i64(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x double>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_mask_v_nxv2f64_nxv2i64(<vscale x 2 x double> *%0, <vscale x 2 x i64> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i64(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x double> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i64(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x double>,
+ i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_v_nxv4f64_nxv4i64(<vscale x 4 x double> *%0, <vscale x 4 x i64> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i64(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x double> %2,
+ i64 %3)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i64(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x double>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_mask_v_nxv4f64_nxv4i64(<vscale x 4 x double> *%0, <vscale x 4 x i64> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i64(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x double> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i64(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x double>,
+ i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_v_nxv8f64_nxv8i64(<vscale x 8 x double> *%0, <vscale x 8 x i64> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i64(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x double> %2,
+ i64 %3)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i64(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x double>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i64(<vscale x 8 x double> *%0, <vscale x 8 x i64> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i64(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x double> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswap.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswap_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoswap.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswap_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswap.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswap_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoswap.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswap_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswap.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswap_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoswap.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswap_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswap.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswap_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoswap.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswap_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i32(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x float>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_v_nxv1f32_nxv1i32(<vscale x 1 x float> *%0, <vscale x 1 x i32> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i32(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x float> %2,
+ i64 %3)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i32(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x float>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_mask_v_nxv1f32_nxv1i32(<vscale x 1 x float> *%0, <vscale x 1 x i32> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i32(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x float> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i32(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x float>,
+ i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_v_nxv2f32_nxv2i32(<vscale x 2 x float> *%0, <vscale x 2 x i32> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i32(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x float> %2,
+ i64 %3)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i32(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x float>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_mask_v_nxv2f32_nxv2i32(<vscale x 2 x float> *%0, <vscale x 2 x i32> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i32(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x float> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i32(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x float>,
+ i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_v_nxv4f32_nxv4i32(<vscale x 4 x float> *%0, <vscale x 4 x i32> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i32(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x float> %2,
+ i64 %3)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i32(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x float>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_mask_v_nxv4f32_nxv4i32(<vscale x 4 x float> *%0, <vscale x 4 x i32> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i32(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x float> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i32(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x float>,
+ i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_v_nxv8f32_nxv8i32(<vscale x 8 x float> *%0, <vscale x 8 x i32> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i32(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x float> %2,
+ i64 %3)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i32(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x float>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_mask_v_nxv8f32_nxv8i32(<vscale x 8 x float> *%0, <vscale x 8 x i32> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i32(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x float> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i32(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x float>,
+ i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_v_nxv16f32_nxv16i32(<vscale x 16 x float> *%0, <vscale x 16 x i32> %1, <vscale x 16 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i32(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x float> %2,
+ i64 %3)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i32(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x float>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i32(<vscale x 16 x float> *%0, <vscale x 16 x i32> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i32(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x float> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i32(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x double>,
+ i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_v_nxv1f64_nxv1i32(<vscale x 1 x double> *%0, <vscale x 1 x i32> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i32(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x double> %2,
+ i64 %3)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i32(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x double>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_mask_v_nxv1f64_nxv1i32(<vscale x 1 x double> *%0, <vscale x 1 x i32> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i32(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x double> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i32(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x double>,
+ i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_v_nxv2f64_nxv2i32(<vscale x 2 x double> *%0, <vscale x 2 x i32> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i32(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x double> %2,
+ i64 %3)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i32(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x double>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_mask_v_nxv2f64_nxv2i32(<vscale x 2 x double> *%0, <vscale x 2 x i32> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i32(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x double> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i32(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x double>,
+ i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_v_nxv4f64_nxv4i32(<vscale x 4 x double> *%0, <vscale x 4 x i32> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i32(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x double> %2,
+ i64 %3)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i32(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x double>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_mask_v_nxv4f64_nxv4i32(<vscale x 4 x double> *%0, <vscale x 4 x i32> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i32(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x double> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i32(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x double>,
+ i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_v_nxv8f64_nxv8i32(<vscale x 8 x double> *%0, <vscale x 8 x i32> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i32(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x double> %2,
+ i64 %3)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i32(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x double>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i32(<vscale x 8 x double> *%0, <vscale x 8 x i32> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i32(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x double> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswap.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswap_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoswap.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswap_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswap.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswap_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoswap.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswap_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswap.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswap_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoswap.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswap_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswap.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswap_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoswap.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswap_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i16(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x float>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_v_nxv1f32_nxv1i16(<vscale x 1 x float> *%0, <vscale x 1 x i16> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i16(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x float> %2,
+ i64 %3)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i16(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x float>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_mask_v_nxv1f32_nxv1i16(<vscale x 1 x float> *%0, <vscale x 1 x i16> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i16(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x float> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i16(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x float>,
+ i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_v_nxv2f32_nxv2i16(<vscale x 2 x float> *%0, <vscale x 2 x i16> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i16(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x float> %2,
+ i64 %3)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i16(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x float>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_mask_v_nxv2f32_nxv2i16(<vscale x 2 x float> *%0, <vscale x 2 x i16> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i16(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x float> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i16(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x float>,
+ i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_v_nxv4f32_nxv4i16(<vscale x 4 x float> *%0, <vscale x 4 x i16> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i16(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x float> %2,
+ i64 %3)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i16(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x float>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_mask_v_nxv4f32_nxv4i16(<vscale x 4 x float> *%0, <vscale x 4 x i16> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i16(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x float> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i16(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x float>,
+ i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_v_nxv8f32_nxv8i16(<vscale x 8 x float> *%0, <vscale x 8 x i16> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i16(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x float> %2,
+ i64 %3)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i16(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x float>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_mask_v_nxv8f32_nxv8i16(<vscale x 8 x float> *%0, <vscale x 8 x i16> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i16(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x float> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i16(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x float>,
+ i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_v_nxv16f32_nxv16i16(<vscale x 16 x float> *%0, <vscale x 16 x i16> %1, <vscale x 16 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i16(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x float> %2,
+ i64 %3)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i16(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x float>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i16(<vscale x 16 x float> *%0, <vscale x 16 x i16> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i16(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x float> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i16(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x double>,
+ i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_v_nxv1f64_nxv1i16(<vscale x 1 x double> *%0, <vscale x 1 x i16> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i16(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x double> %2,
+ i64 %3)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i16(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x double>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_mask_v_nxv1f64_nxv1i16(<vscale x 1 x double> *%0, <vscale x 1 x i16> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i16(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x double> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i16(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x double>,
+ i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_v_nxv2f64_nxv2i16(<vscale x 2 x double> *%0, <vscale x 2 x i16> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i16(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x double> %2,
+ i64 %3)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i16(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x double>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_mask_v_nxv2f64_nxv2i16(<vscale x 2 x double> *%0, <vscale x 2 x i16> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i16(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x double> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i16(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x double>,
+ i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_v_nxv4f64_nxv4i16(<vscale x 4 x double> *%0, <vscale x 4 x i16> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i16(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x double> %2,
+ i64 %3)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i16(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x double>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_mask_v_nxv4f64_nxv4i16(<vscale x 4 x double> *%0, <vscale x 4 x i16> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i16(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x double> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i16(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x double>,
+ i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_v_nxv8f64_nxv8i16(<vscale x 8 x double> *%0, <vscale x 8 x i16> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i16(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x double> %2,
+ i64 %3)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i16(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x double>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i16(<vscale x 8 x double> *%0, <vscale x 8 x i16> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i16(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x double> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoswap_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoswap_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoswap_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoswap_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswap.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswap_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoswap.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoswap_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswap.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswap_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoswap.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoswap_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswap.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswap_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoswap.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoswap_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswap.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswap_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoswap.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoswap_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i8(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x float>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_v_nxv1f32_nxv1i8(<vscale x 1 x float> *%0, <vscale x 1 x i8> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.nxv1f32.nxv1i8(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x float> %2,
+ i64 %3)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i8(
+ <vscale x 1 x float>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x float>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x float> @intrinsic_vamoswap_mask_v_nxv1f32_nxv1i8(<vscale x 1 x float> *%0, <vscale x 1 x i8> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x float> @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i8(
+ <vscale x 1 x float> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x float> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i8(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x float>,
+ i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_v_nxv2f32_nxv2i8(<vscale x 2 x float> *%0, <vscale x 2 x i8> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.nxv2f32.nxv2i8(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x float> %2,
+ i64 %3)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i8(
+ <vscale x 2 x float>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x float>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x float> @intrinsic_vamoswap_mask_v_nxv2f32_nxv2i8(<vscale x 2 x float> *%0, <vscale x 2 x i8> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x float> @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i8(
+ <vscale x 2 x float> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x float> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i8(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x float>,
+ i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_v_nxv4f32_nxv4i8(<vscale x 4 x float> *%0, <vscale x 4 x i8> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.nxv4f32.nxv4i8(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x float> %2,
+ i64 %3)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i8(
+ <vscale x 4 x float>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x float>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x float> @intrinsic_vamoswap_mask_v_nxv4f32_nxv4i8(<vscale x 4 x float> *%0, <vscale x 4 x i8> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x float> @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i8(
+ <vscale x 4 x float> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x float> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i8(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x float>,
+ i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_v_nxv8f32_nxv8i8(<vscale x 8 x float> *%0, <vscale x 8 x i8> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.nxv8f32.nxv8i8(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x float> %2,
+ i64 %3)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i8(
+ <vscale x 8 x float>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x float>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x float> @intrinsic_vamoswap_mask_v_nxv8f32_nxv8i8(<vscale x 8 x float> *%0, <vscale x 8 x i8> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x float> @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i8(
+ <vscale x 8 x float> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x float> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i8(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x float>,
+ i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_v_nxv16f32_nxv16i8(<vscale x 16 x float> *%0, <vscale x 16 x i8> %1, <vscale x 16 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.nxv16f32.nxv16i8(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x float> %2,
+ i64 %3)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i8(
+ <vscale x 16 x float>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x float>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x float> @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i8(<vscale x 16 x float> *%0, <vscale x 16 x i8> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x float> @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i8(
+ <vscale x 16 x float> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x float> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i8(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x double>,
+ i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_v_nxv1f64_nxv1i8(<vscale x 1 x double> *%0, <vscale x 1 x i8> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.nxv1f64.nxv1i8(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x double> %2,
+ i64 %3)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i8(
+ <vscale x 1 x double>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x double>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x double> @intrinsic_vamoswap_mask_v_nxv1f64_nxv1i8(<vscale x 1 x double> *%0, <vscale x 1 x i8> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x double> @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i8(
+ <vscale x 1 x double> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x double> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i8(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x double>,
+ i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_v_nxv2f64_nxv2i8(<vscale x 2 x double> *%0, <vscale x 2 x i8> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.nxv2f64.nxv2i8(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x double> %2,
+ i64 %3)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i8(
+ <vscale x 2 x double>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x double>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x double> @intrinsic_vamoswap_mask_v_nxv2f64_nxv2i8(<vscale x 2 x double> *%0, <vscale x 2 x i8> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x double> @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i8(
+ <vscale x 2 x double> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x double> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i8(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x double>,
+ i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_v_nxv4f64_nxv4i8(<vscale x 4 x double> *%0, <vscale x 4 x i8> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.nxv4f64.nxv4i8(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x double> %2,
+ i64 %3)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i8(
+ <vscale x 4 x double>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x double>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x double> @intrinsic_vamoswap_mask_v_nxv4f64_nxv4i8(<vscale x 4 x double> *%0, <vscale x 4 x i8> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x double> @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i8(
+ <vscale x 4 x double> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x double> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i8(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x double>,
+ i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_v_nxv8f64_nxv8i8(<vscale x 8 x double> *%0, <vscale x 8 x i8> %1, <vscale x 8 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.nxv8f64.nxv8i8(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x double> %2,
+ i64 %3)
+
+ ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i8(
+ <vscale x 8 x double>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x double>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x double> @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i8(<vscale x 8 x double> *%0, <vscale x 8 x i8> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x double> @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i8(
+ <vscale x 8 x double> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x double> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll
new file mode 100644
index 000000000000..ddf94e2fa226
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll
@@ -0,0 +1,734 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i32);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i32);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i32);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i32);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i32 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i32);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i32 %4)
+
+ ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll
new file mode 100644
index 000000000000..7739cc68cbbb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll
@@ -0,0 +1,1714 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zvamo -verify-machineinstrs \
+; RUN: --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_mask_v_nxv1i32_nxv1i64(<vscale x 1 x i32> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i64(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_mask_v_nxv2i32_nxv2i64(<vscale x 2 x i32> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv1r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i64(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_mask_v_nxv4i32_nxv4i64(<vscale x 4 x i32> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv2r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i64(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei64.v v28, (a0), v16, v28
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_mask_v_nxv8i32_nxv8i64(<vscale x 8 x i32> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei64.v v28, (a0), v16, v28, v0.t
+; CHECK-NEXT: vmv4r.v v16, v28
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i64(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxor.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxor_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoxorei64.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoxor.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxor_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> *%0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i64_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoxorei64.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i64(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxor.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxor_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoxorei64.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoxor.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxor_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> *%0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i64_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoxorei64.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i64(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i64> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxor.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxor_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoxorei64.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoxor.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxor_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> *%0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i64_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoxorei64.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i64(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i64> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxor.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxor_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoxorei64.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoxor.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxor_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> *%0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i64_nxv8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoxorei64.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i64(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i64> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i32(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i32(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i32(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i32(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> *%0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i32(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i32> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxor.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxor_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoxor.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxor_mask_v_nxv1i64_nxv1i32(<vscale x 1 x i64> *%0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i64_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i32(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i32> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxor.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxor_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoxor.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxor_mask_v_nxv2i64_nxv2i32(<vscale x 2 x i64> *%0, <vscale x 2 x i32> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i64_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i32(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i32> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxor.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxor_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoxor.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxor_mask_v_nxv4i64_nxv4i32(<vscale x 4 x i64> *%0, <vscale x 4 x i32> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i64_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i32(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i32> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxor.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxor_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoxor.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxor_mask_v_nxv8i64_nxv8i32(<vscale x 8 x i64> *%0, <vscale x 8 x i32> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i64_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i32(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i32> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_mask_v_nxv1i32_nxv1i16(<vscale x 1 x i32> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i16(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_mask_v_nxv2i32_nxv2i16(<vscale x 2 x i32> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i16(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_mask_v_nxv4i32_nxv4i16(<vscale x 4 x i32> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i16(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_mask_v_nxv8i32_nxv8i16(<vscale x 8 x i32> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i16(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i16>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i16(<vscale x 16 x i32> *%0, <vscale x 16 x i16> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i16(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i16> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxor.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxor_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoxor.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i16>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxor_mask_v_nxv1i64_nxv1i16(<vscale x 1 x i64> *%0, <vscale x 1 x i16> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i64_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i16(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i16> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxor.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxor_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoxor.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i16>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxor_mask_v_nxv2i64_nxv2i16(<vscale x 2 x i64> *%0, <vscale x 2 x i16> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i64_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i16(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i16> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxor.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxor_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoxor.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i16>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxor_mask_v_nxv4i64_nxv4i16(<vscale x 4 x i64> *%0, <vscale x 4 x i16> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i64_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i16(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i16> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxor.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxor_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoxor.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i16>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxor_mask_v_nxv8i64_nxv8i16(<vscale x 8 x i64> *%0, <vscale x 8 x i16> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i64_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i16(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i16> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i32>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i32> @intrinsic_vamoxor_mask_v_nxv1i32_nxv1i8(<vscale x 1 x i32> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i32> @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i8(
+ <vscale x 1 x i32> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i32> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i32>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i32> @intrinsic_vamoxor_mask_v_nxv2i32_nxv2i8(<vscale x 2 x i32> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i32> @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i8(
+ <vscale x 2 x i32> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i32> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i32>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i32> @intrinsic_vamoxor_mask_v_nxv4i32_nxv4i8(<vscale x 4 x i32> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i32> @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i8(
+ <vscale x 4 x i32> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i32> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i32>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i32> @intrinsic_vamoxor_mask_v_nxv8i32_nxv8i8(<vscale x 8 x i32> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i32> @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i8(
+ <vscale x 8 x i32> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i32> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ i64 %3)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32>*,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i32>,
+ <vscale x 16 x i1>,
+ i64);
+
+define <vscale x 16 x i32> @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i8(<vscale x 16 x i32> *%0, <vscale x 16 x i8> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu
+; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 16 x i32> @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i8(
+ <vscale x 16 x i32> *%0,
+ <vscale x 16 x i8> %1,
+ <vscale x 16 x i32> %2,
+ <vscale x 16 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxor.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxor_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoxor.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64>*,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i64>,
+ <vscale x 1 x i1>,
+ i64);
+
+define <vscale x 1 x i64> @intrinsic_vamoxor_mask_v_nxv1i64_nxv1i8(<vscale x 1 x i64> *%0, <vscale x 1 x i8> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i64_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t
+; CHECK-NEXT: vmv1r.v v16, v17
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 1 x i64> @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i8(
+ <vscale x 1 x i64> *%0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i64> %2,
+ <vscale x 1 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxor.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxor_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoxor.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64>*,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i64>,
+ <vscale x 2 x i1>,
+ i64);
+
+define <vscale x 2 x i64> @intrinsic_vamoxor_mask_v_nxv2i64_nxv2i8(<vscale x 2 x i64> *%0, <vscale x 2 x i8> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i64_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18, v0.t
+; CHECK-NEXT: vmv2r.v v16, v18
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 2 x i64> @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i8(
+ <vscale x 2 x i64> *%0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i64> %2,
+ <vscale x 2 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxor.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxor_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoxor.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64>*,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i64>,
+ <vscale x 4 x i1>,
+ i64);
+
+define <vscale x 4 x i64> @intrinsic_vamoxor_mask_v_nxv4i64_nxv4i8(<vscale x 4 x i64> *%0, <vscale x 4 x i8> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i64_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20, v0.t
+; CHECK-NEXT: vmv4r.v v16, v20
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 4 x i64> @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i8(
+ <vscale x 4 x i64> *%0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i64> %2,
+ <vscale x 4 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxor.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxor_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoxor.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ i64 %3)
+
+ ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64>*,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i64>,
+ <vscale x 8 x i1>,
+ i64);
+
+define <vscale x 8 x i64> @intrinsic_vamoxor_mask_v_nxv8i64_nxv8i8(<vscale x 8 x i64> *%0, <vscale x 8 x i8> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i64_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu
+; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: jalr zero, 0(ra)
+entry:
+ %a = call <vscale x 8 x i64> @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i8(
+ <vscale x 8 x i64> *%0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i64> %2,
+ <vscale x 8 x i1> %3,
+ i64 %4)
+
+ ret <vscale x 8 x i64> %a
+}
More information about the llvm-branch-commits
mailing list