[llvm-branch-commits] [llvm] 8a53a73 - [RISCV][NFC] Regenerate Calling Convention Tests
Sam Elliott via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jan 14 14:40:46 PST 2021
Author: Sam Elliott
Date: 2021-01-14T22:35:17Z
New Revision: 8a53a7375a86a5a89ba124de9e17aa5701544104
URL: https://github.com/llvm/llvm-project/commit/8a53a7375a86a5a89ba124de9e17aa5701544104
DIFF: https://github.com/llvm/llvm-project/commit/8a53a7375a86a5a89ba124de9e17aa5701544104.diff
LOG: [RISCV][NFC] Regenerate Calling Convention Tests
This regenerates these tests using utils/update_llc_test_checks.py so
that future changes in this area don't have the noise of lots of `@plt`
lines being added.
I also removed the `nounwind`s from the stack-realignment.ll test to
increase coverage on the generated call frame information.
Added:
Modified:
llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
llvm/test/CodeGen/RISCV/stack-realignment.ll
llvm/test/CodeGen/RISCV/vararg.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
index e213d1f3b594..d8d904ac85c6 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
@@ -629,7 +629,7 @@ define void @caller() nounwind {
; ILP32-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
; ILP32-NEXT: flw ft0, 124(s1)
; ILP32-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
-; ILP32-NEXT: call callee
+; ILP32-NEXT: call callee at plt
; ILP32-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload
; ILP32-NEXT: fsw ft0, 124(s1)
; ILP32-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
@@ -772,7 +772,7 @@ define void @caller() nounwind {
; LP64-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; LP64-NEXT: flw ft0, 124(s1)
; LP64-NEXT: fsw ft0, 8(sp) # 4-byte Folded Spill
-; LP64-NEXT: call callee
+; LP64-NEXT: call callee at plt
; LP64-NEXT: flw ft0, 8(sp) # 4-byte Folded Reload
; LP64-NEXT: fsw ft0, 124(s1)
; LP64-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
@@ -915,7 +915,7 @@ define void @caller() nounwind {
; ILP32F-NEXT: flw fs5, 116(s1)
; ILP32F-NEXT: flw fs6, 120(s1)
; ILP32F-NEXT: flw fs7, 124(s1)
-; ILP32F-NEXT: call callee
+; ILP32F-NEXT: call callee at plt
; ILP32F-NEXT: fsw fs7, 124(s1)
; ILP32F-NEXT: fsw fs6, 120(s1)
; ILP32F-NEXT: fsw fs5, 116(s1)
@@ -1058,7 +1058,7 @@ define void @caller() nounwind {
; LP64F-NEXT: flw fs5, 116(s1)
; LP64F-NEXT: flw fs6, 120(s1)
; LP64F-NEXT: flw fs7, 124(s1)
-; LP64F-NEXT: call callee
+; LP64F-NEXT: call callee at plt
; LP64F-NEXT: fsw fs7, 124(s1)
; LP64F-NEXT: fsw fs6, 120(s1)
; LP64F-NEXT: fsw fs5, 116(s1)
@@ -1201,7 +1201,7 @@ define void @caller() nounwind {
; ILP32D-NEXT: flw fs5, 116(s1)
; ILP32D-NEXT: flw fs6, 120(s1)
; ILP32D-NEXT: flw fs7, 124(s1)
-; ILP32D-NEXT: call callee
+; ILP32D-NEXT: call callee at plt
; ILP32D-NEXT: fsw fs7, 124(s1)
; ILP32D-NEXT: fsw fs6, 120(s1)
; ILP32D-NEXT: fsw fs5, 116(s1)
@@ -1344,7 +1344,7 @@ define void @caller() nounwind {
; LP64D-NEXT: flw fs5, 116(s1)
; LP64D-NEXT: flw fs6, 120(s1)
; LP64D-NEXT: flw fs7, 124(s1)
-; LP64D-NEXT: call callee
+; LP64D-NEXT: call callee at plt
; LP64D-NEXT: fsw fs7, 124(s1)
; LP64D-NEXT: fsw fs6, 120(s1)
; LP64D-NEXT: fsw fs5, 116(s1)
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
index efd0455a821d..e18cb5953492 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
@@ -433,7 +433,7 @@ define void @caller() nounwind {
; ILP32-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; ILP32-NEXT: fld ft0, 248(s1)
; ILP32-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
-; ILP32-NEXT: call callee
+; ILP32-NEXT: call callee at plt
; ILP32-NEXT: fld ft0, 0(sp) # 8-byte Folded Reload
; ILP32-NEXT: fsd ft0, 248(s1)
; ILP32-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
@@ -576,7 +576,7 @@ define void @caller() nounwind {
; LP64-NEXT: fsd ft0, 16(sp) # 8-byte Folded Spill
; LP64-NEXT: fld ft0, 248(s1)
; LP64-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
-; LP64-NEXT: call callee
+; LP64-NEXT: call callee at plt
; LP64-NEXT: fld ft0, 8(sp) # 8-byte Folded Reload
; LP64-NEXT: fsd ft0, 248(s1)
; LP64-NEXT: fld ft0, 16(sp) # 8-byte Folded Reload
@@ -719,7 +719,7 @@ define void @caller() nounwind {
; ILP32D-NEXT: fld fs5, 232(s1)
; ILP32D-NEXT: fld fs6, 240(s1)
; ILP32D-NEXT: fld fs7, 248(s1)
-; ILP32D-NEXT: call callee
+; ILP32D-NEXT: call callee at plt
; ILP32D-NEXT: fsd fs7, 248(s1)
; ILP32D-NEXT: fsd fs6, 240(s1)
; ILP32D-NEXT: fsd fs5, 232(s1)
@@ -862,7 +862,7 @@ define void @caller() nounwind {
; LP64D-NEXT: fld fs5, 232(s1)
; LP64D-NEXT: fld fs6, 240(s1)
; LP64D-NEXT: fld fs7, 248(s1)
-; LP64D-NEXT: call callee
+; LP64D-NEXT: call callee at plt
; LP64D-NEXT: fsd fs7, 248(s1)
; LP64D-NEXT: fsd fs6, 240(s1)
; LP64D-NEXT: fsd fs5, 232(s1)
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
index 76c87ed1aa7d..024d015e4f54 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -552,7 +552,7 @@ define void @caller() nounwind {
; RV32I-NEXT: lw s11, 116(s1)
; RV32I-NEXT: lw s2, 120(s1)
; RV32I-NEXT: lw s3, 124(s1)
-; RV32I-NEXT: call callee
+; RV32I-NEXT: call callee at plt
; RV32I-NEXT: sw s3, 124(s1)
; RV32I-NEXT: sw s2, 120(s1)
; RV32I-NEXT: sw s11, 116(s1)
@@ -697,7 +697,7 @@ define void @caller() nounwind {
; RV32I-WITH-FP-NEXT: lw s4, 116(s1)
; RV32I-WITH-FP-NEXT: lw s5, 120(s1)
; RV32I-WITH-FP-NEXT: lw s7, 124(s1)
-; RV32I-WITH-FP-NEXT: call callee
+; RV32I-WITH-FP-NEXT: call callee at plt
; RV32I-WITH-FP-NEXT: sw s7, 124(s1)
; RV32I-WITH-FP-NEXT: sw s5, 120(s1)
; RV32I-WITH-FP-NEXT: sw s4, 116(s1)
@@ -841,7 +841,7 @@ define void @caller() nounwind {
; RV64I-NEXT: lw s11, 116(s1)
; RV64I-NEXT: lw s2, 120(s1)
; RV64I-NEXT: lw s3, 124(s1)
-; RV64I-NEXT: call callee
+; RV64I-NEXT: call callee at plt
; RV64I-NEXT: sw s3, 124(s1)
; RV64I-NEXT: sw s2, 120(s1)
; RV64I-NEXT: sw s11, 116(s1)
@@ -986,7 +986,7 @@ define void @caller() nounwind {
; RV64I-WITH-FP-NEXT: lw s4, 116(s1)
; RV64I-WITH-FP-NEXT: lw s5, 120(s1)
; RV64I-WITH-FP-NEXT: lw s7, 124(s1)
-; RV64I-WITH-FP-NEXT: call callee
+; RV64I-WITH-FP-NEXT: call callee at plt
; RV64I-WITH-FP-NEXT: sw s7, 124(s1)
; RV64I-WITH-FP-NEXT: sw s5, 120(s1)
; RV64I-WITH-FP-NEXT: sw s4, 116(s1)
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
index 6125bcfc2902..c9d59e229bd8 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
@@ -63,7 +63,7 @@ define i32 @caller_double_in_regs() nounwind {
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: lui a2, 262144
; RV32I-FPELIM-NEXT: mv a1, zero
-; RV32I-FPELIM-NEXT: call callee_double_in_regs
+; RV32I-FPELIM-NEXT: call callee_double_in_regs at plt
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
@@ -77,7 +77,7 @@ define i32 @caller_double_in_regs() nounwind {
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: lui a2, 262144
; RV32I-WITHFP-NEXT: mv a1, zero
-; RV32I-WITHFP-NEXT: call callee_double_in_regs
+; RV32I-WITHFP-NEXT: call callee_double_in_regs at plt
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
@@ -180,7 +180,7 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14
; RV32I-FPELIM-NEXT: sw t0, 32(sp)
-; RV32I-FPELIM-NEXT: call callee_aligned_stack
+; RV32I-FPELIM-NEXT: call callee_aligned_stack at plt
; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
@@ -226,7 +226,7 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14
; RV32I-WITHFP-NEXT: sw t0, -32(s0)
-; RV32I-WITHFP-NEXT: call callee_aligned_stack
+; RV32I-WITHFP-NEXT: call callee_aligned_stack at plt
; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 64
@@ -265,7 +265,7 @@ define i64 @caller_small_scalar_ret() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-FPELIM-NEXT: call callee_small_scalar_ret
+; RV32I-FPELIM-NEXT: call callee_small_scalar_ret at plt
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
@@ -276,7 +276,7 @@ define i64 @caller_small_scalar_ret() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: call callee_small_scalar_ret
+; RV32I-WITHFP-NEXT: call callee_small_scalar_ret at plt
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
index f76c35252f02..978bc9965de7 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
@@ -54,7 +54,7 @@ define i32 @caller_i64_in_regs() nounwind {
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: mv a2, zero
-; RV32I-FPELIM-NEXT: call callee_i64_in_regs
+; RV32I-FPELIM-NEXT: call callee_i64_in_regs at plt
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
@@ -68,7 +68,7 @@ define i32 @caller_i64_in_regs() nounwind {
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: mv a2, zero
-; RV32I-WITHFP-NEXT: call callee_i64_in_regs
+; RV32I-WITHFP-NEXT: call callee_i64_in_regs at plt
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
@@ -155,7 +155,7 @@ define i32 @caller_many_scalars() nounwind {
; RV32I-FPELIM-NEXT: addi a7, zero, 7
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: mv a4, zero
-; RV32I-FPELIM-NEXT: call callee_many_scalars
+; RV32I-FPELIM-NEXT: call callee_many_scalars at plt
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
@@ -177,7 +177,7 @@ define i32 @caller_many_scalars() nounwind {
; RV32I-WITHFP-NEXT: addi a7, zero, 7
; RV32I-WITHFP-NEXT: sw zero, 0(sp)
; RV32I-WITHFP-NEXT: mv a4, zero
-; RV32I-WITHFP-NEXT: call callee_many_scalars
+; RV32I-WITHFP-NEXT: call callee_many_scalars at plt
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
@@ -259,7 +259,7 @@ define i32 @caller_large_scalars() nounwind {
; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-FPELIM-NEXT: mv a1, sp
; RV32I-FPELIM-NEXT: sw a2, 24(sp)
-; RV32I-FPELIM-NEXT: call callee_large_scalars
+; RV32I-FPELIM-NEXT: call callee_large_scalars at plt
; RV32I-FPELIM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
@@ -282,7 +282,7 @@ define i32 @caller_large_scalars() nounwind {
; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: addi a1, s0, -48
; RV32I-WITHFP-NEXT: sw a2, -24(s0)
-; RV32I-WITHFP-NEXT: call callee_large_scalars
+; RV32I-WITHFP-NEXT: call callee_large_scalars at plt
; RV32I-WITHFP-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 48
@@ -377,7 +377,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-NEXT: addi a6, zero, 7
; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: sw t0, 40(sp)
-; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs
+; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs at plt
; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
@@ -410,7 +410,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: addi a6, zero, 7
; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: sw t0, -24(s0)
-; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs
+; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs at plt
; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 64
@@ -495,7 +495,7 @@ define i32 @caller_small_coerced_struct() nounwind {
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
-; RV32I-FPELIM-NEXT: call callee_small_coerced_struct
+; RV32I-FPELIM-NEXT: call callee_small_coerced_struct at plt
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
@@ -508,7 +508,7 @@ define i32 @caller_small_coerced_struct() nounwind {
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
-; RV32I-WITHFP-NEXT: call callee_small_coerced_struct
+; RV32I-WITHFP-NEXT: call callee_small_coerced_struct at plt
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
@@ -568,7 +568,7 @@ define i32 @caller_large_struct() nounwind {
; RV32I-FPELIM-NEXT: sw a2, 16(sp)
; RV32I-FPELIM-NEXT: sw a3, 20(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 8
-; RV32I-FPELIM-NEXT: call callee_large_struct
+; RV32I-FPELIM-NEXT: call callee_large_struct at plt
; RV32I-FPELIM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
@@ -592,7 +592,7 @@ define i32 @caller_large_struct() nounwind {
; RV32I-WITHFP-NEXT: sw a2, -32(s0)
; RV32I-WITHFP-NEXT: sw a3, -28(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, -40
-; RV32I-WITHFP-NEXT: call callee_large_struct
+; RV32I-WITHFP-NEXT: call callee_large_struct at plt
; RV32I-WITHFP-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 48
@@ -701,7 +701,7 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14
; RV32I-FPELIM-NEXT: sw t0, 32(sp)
-; RV32I-FPELIM-NEXT: call callee_aligned_stack
+; RV32I-FPELIM-NEXT: call callee_aligned_stack at plt
; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
@@ -744,7 +744,7 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14
; RV32I-WITHFP-NEXT: sw t0, -32(s0)
-; RV32I-WITHFP-NEXT: call callee_aligned_stack
+; RV32I-WITHFP-NEXT: call callee_aligned_stack at plt
; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 64
@@ -787,7 +787,7 @@ define i32 @caller_small_scalar_ret() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-FPELIM-NEXT: call callee_small_scalar_ret
+; RV32I-FPELIM-NEXT: call callee_small_scalar_ret at plt
; RV32I-FPELIM-NEXT: lui a2, 56
; RV32I-FPELIM-NEXT: addi a2, a2, 580
; RV32I-FPELIM-NEXT: xor a1, a1, a2
@@ -806,7 +806,7 @@ define i32 @caller_small_scalar_ret() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: call callee_small_scalar_ret
+; RV32I-WITHFP-NEXT: call callee_small_scalar_ret at plt
; RV32I-WITHFP-NEXT: lui a2, 56
; RV32I-WITHFP-NEXT: addi a2, a2, 580
; RV32I-WITHFP-NEXT: xor a1, a1, a2
@@ -854,7 +854,7 @@ define i32 @caller_small_struct_ret() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-FPELIM-NEXT: call callee_small_struct_ret
+; RV32I-FPELIM-NEXT: call callee_small_struct_ret at plt
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
@@ -866,7 +866,7 @@ define i32 @caller_small_struct_ret() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: call callee_small_struct_ret
+; RV32I-WITHFP-NEXT: call callee_small_struct_ret at plt
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -916,7 +916,7 @@ define void @caller_large_scalar_ret() nounwind {
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: mv a0, sp
-; RV32I-FPELIM-NEXT: call callee_large_scalar_ret
+; RV32I-FPELIM-NEXT: call callee_large_scalar_ret at plt
; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
@@ -928,7 +928,7 @@ define void @caller_large_scalar_ret() nounwind {
; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: addi a0, s0, -32
-; RV32I-WITHFP-NEXT: call callee_large_scalar_ret
+; RV32I-WITHFP-NEXT: call callee_large_scalar_ret at plt
; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 32
@@ -987,7 +987,7 @@ define i32 @caller_large_struct_ret() nounwind {
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, sp, 8
-; RV32I-FPELIM-NEXT: call callee_large_struct_ret
+; RV32I-FPELIM-NEXT: call callee_large_struct_ret at plt
; RV32I-FPELIM-NEXT: lw a0, 8(sp)
; RV32I-FPELIM-NEXT: lw a1, 20(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
@@ -1002,7 +1002,7 @@ define i32 @caller_large_struct_ret() nounwind {
; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: addi a0, s0, -24
-; RV32I-WITHFP-NEXT: call callee_large_struct_ret
+; RV32I-WITHFP-NEXT: call callee_large_struct_ret at plt
; RV32I-WITHFP-NEXT: lw a0, -24(s0)
; RV32I-WITHFP-NEXT: lw a1, -12(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
index 500a158b4961..67d3bde9444b 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
@@ -55,7 +55,7 @@ define i32 @caller_float_in_regs() nounwind {
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: lui a1, 262144
-; RV32I-FPELIM-NEXT: call callee_float_in_regs
+; RV32I-FPELIM-NEXT: call callee_float_in_regs at plt
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
@@ -68,7 +68,7 @@ define i32 @caller_float_in_regs() nounwind {
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: lui a1, 262144
-; RV32I-WITHFP-NEXT: call callee_float_in_regs
+; RV32I-WITHFP-NEXT: call callee_float_in_regs at plt
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
@@ -117,7 +117,7 @@ define i32 @caller_float_on_stack() nounwind {
; RV32I-FPELIM-NEXT: mv a3, zero
; RV32I-FPELIM-NEXT: mv a5, zero
; RV32I-FPELIM-NEXT: mv a7, zero
-; RV32I-FPELIM-NEXT: call callee_float_on_stack
+; RV32I-FPELIM-NEXT: call callee_float_on_stack at plt
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
@@ -138,7 +138,7 @@ define i32 @caller_float_on_stack() nounwind {
; RV32I-WITHFP-NEXT: mv a3, zero
; RV32I-WITHFP-NEXT: mv a5, zero
; RV32I-WITHFP-NEXT: mv a7, zero
-; RV32I-WITHFP-NEXT: call callee_float_on_stack
+; RV32I-WITHFP-NEXT: call callee_float_on_stack at plt
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
@@ -172,7 +172,7 @@ define i32 @caller_tiny_scalar_ret() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret
+; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret at plt
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
@@ -183,7 +183,7 @@ define i32 @caller_tiny_scalar_ret() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret
+; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret at plt
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
index 80b0d9695feb..ee08a851a70b 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
@@ -25,7 +25,7 @@ define i32 @caller_double_in_fpr() nounwind {
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI1_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI1_0)(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1
-; RV32-ILP32D-NEXT: call callee_double_in_fpr
+; RV32-ILP32D-NEXT: call callee_double_in_fpr at plt
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
@@ -63,7 +63,7 @@ define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero
-; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs
+; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs at plt
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
@@ -114,7 +114,7 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI5_7)(a0)
; RV32-ILP32D-NEXT: lui a1, 262688
; RV32-ILP32D-NEXT: mv a0, zero
-; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs
+; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs at plt
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
@@ -173,7 +173,7 @@ define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero
-; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs
+; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs at plt
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
@@ -230,7 +230,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero
-; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs
+; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs at plt
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
@@ -254,7 +254,7 @@ define i32 @caller_double_ret() nounwind {
; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32D-NEXT: call callee_double_ret
+; RV32-ILP32D-NEXT: call callee_double_ret at plt
; RV32-ILP32D-NEXT: fsd fa0, 0(sp)
; RV32-ILP32D-NEXT: lw a0, 0(sp)
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
index f571c0a7a2e2..2ceda820780e 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
@@ -28,7 +28,7 @@ define i32 @caller_float_in_fpr() nounwind {
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32-ILP32FD-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
; RV32-ILP32FD-NEXT: addi a0, zero, 1
-; RV32-ILP32FD-NEXT: call callee_float_in_fpr
+; RV32-ILP32FD-NEXT: call callee_float_in_fpr at plt
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret
@@ -66,7 +66,7 @@ define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: mv a7, zero
-; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs
+; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs at plt
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret
@@ -112,7 +112,7 @@ define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_7)
; RV32-ILP32FD-NEXT: flw fa7, %lo(.LCPI5_7)(a0)
; RV32-ILP32FD-NEXT: lui a0, 266496
-; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs
+; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs at plt
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret
@@ -167,7 +167,7 @@ define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: mv a7, zero
-; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs
+; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs at plt
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret
@@ -191,7 +191,7 @@ define i32 @caller_float_ret() nounwind {
; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32-ILP32FD-NEXT: call callee_float_ret
+; RV32-ILP32FD-NEXT: call callee_float_ret at plt
; RV32-ILP32FD-NEXT: fmv.x.w a0, fa0
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
index e415b40411c9..0dbffeb95a3c 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
@@ -36,7 +36,7 @@ define i64 @caller_double_in_regs() nounwind {
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: slli a1, a0, 62
; RV64I-NEXT: addi a0, zero, 1
-; RV64I-NEXT: call callee_double_in_regs
+; RV64I-NEXT: call callee_double_in_regs at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -58,7 +58,7 @@ define i64 @caller_double_ret() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call callee_double_ret
+; RV64I-NEXT: call callee_double_ret at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
index f1fdd0de6730..65a152b44dc7 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
@@ -35,7 +35,7 @@ define i64 @caller_i128_in_regs() nounwind {
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: mv a2, zero
-; RV64I-NEXT: call callee_i128_in_regs
+; RV64I-NEXT: call callee_i128_in_regs at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -94,7 +94,7 @@ define i32 @caller_many_scalars() nounwind {
; RV64I-NEXT: addi a7, zero, 7
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: mv a4, zero
-; RV64I-NEXT: call callee_many_scalars
+; RV64I-NEXT: call callee_many_scalars at plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
@@ -146,7 +146,7 @@ define i64 @caller_large_scalars() nounwind {
; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: sd a2, 32(sp)
-; RV64I-NEXT: call callee_large_scalars
+; RV64I-NEXT: call callee_large_scalars at plt
; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: ret
@@ -211,7 +211,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: addi a6, zero, 7
; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: sd t0, 48(sp)
-; RV64I-NEXT: call callee_large_scalars_exhausted_regs
+; RV64I-NEXT: call callee_large_scalars_exhausted_regs at plt
; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: ret
@@ -262,7 +262,7 @@ define i64 @caller_small_coerced_struct() nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2
-; RV64I-NEXT: call callee_small_coerced_struct
+; RV64I-NEXT: call callee_small_coerced_struct at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -307,7 +307,7 @@ define i64 @caller_large_struct() nounwind {
; RV64I-NEXT: sd a2, 24(sp)
; RV64I-NEXT: sd a3, 32(sp)
; RV64I-NEXT: addi a0, sp, 8
-; RV64I-NEXT: call callee_large_struct
+; RV64I-NEXT: call callee_large_struct at plt
; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: ret
@@ -379,7 +379,7 @@ define void @caller_aligned_stack() nounwind {
; RV64I-NEXT: addi a7, zero, 7
; RV64I-NEXT: sd a6, 0(sp)
; RV64I-NEXT: mv a6, zero
-; RV64I-NEXT: call callee_aligned_stack
+; RV64I-NEXT: call callee_aligned_stack at plt
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret
@@ -404,7 +404,7 @@ define i64 @caller_small_scalar_ret() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call callee_small_scalar_ret
+; RV64I-NEXT: call callee_small_scalar_ret at plt
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: xori a0, a0, -2
; RV64I-NEXT: or a0, a0, a1
@@ -434,7 +434,7 @@ define i64 @caller_small_struct_ret() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: call callee_small_struct_ret
+; RV64I-NEXT: call callee_small_struct_ret at plt
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
@@ -469,7 +469,7 @@ define void @caller_large_scalar_ret() nounwind {
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp
-; RV64I-NEXT: call callee_large_scalar_ret
+; RV64I-NEXT: call callee_large_scalar_ret at plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
@@ -512,7 +512,7 @@ define i64 @caller_large_struct_ret() nounwind {
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, sp, 8
-; RV64I-NEXT: call callee_large_struct_ret
+; RV64I-NEXT: call callee_large_struct_ret at plt
; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a1, 32(sp)
; RV64I-NEXT: add a0, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
index 38df7f42a4c5..ca7d7b9491b2 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
@@ -57,7 +57,7 @@ define i64 @caller_float_in_regs() nounwind {
; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: addi a0, zero, 1
; RV64I-FPELIM-NEXT: lui a1, 262144
-; RV64I-FPELIM-NEXT: call callee_float_in_regs
+; RV64I-FPELIM-NEXT: call callee_float_in_regs at plt
; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret
@@ -70,7 +70,7 @@ define i64 @caller_float_in_regs() nounwind {
; RV64I-WITHFP-NEXT: addi s0, sp, 16
; RV64I-WITHFP-NEXT: addi a0, zero, 1
; RV64I-WITHFP-NEXT: lui a1, 262144
-; RV64I-WITHFP-NEXT: call callee_float_in_regs
+; RV64I-WITHFP-NEXT: call callee_float_in_regs at plt
; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 16
@@ -118,7 +118,7 @@ define i64 @caller_float_on_stack() nounwind {
; RV64I-FPELIM-NEXT: mv a3, zero
; RV64I-FPELIM-NEXT: mv a5, zero
; RV64I-FPELIM-NEXT: mv a7, zero
-; RV64I-FPELIM-NEXT: call callee_float_on_stack
+; RV64I-FPELIM-NEXT: call callee_float_on_stack at plt
; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret
@@ -139,7 +139,7 @@ define i64 @caller_float_on_stack() nounwind {
; RV64I-WITHFP-NEXT: mv a3, zero
; RV64I-WITHFP-NEXT: mv a5, zero
; RV64I-WITHFP-NEXT: mv a7, zero
-; RV64I-WITHFP-NEXT: call callee_float_on_stack
+; RV64I-WITHFP-NEXT: call callee_float_on_stack at plt
; RV64I-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 32
@@ -176,7 +176,7 @@ define i64 @caller_tiny_scalar_ret() nounwind {
; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret
+; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret at plt
; RV64I-FPELIM-NEXT: sext.w a0, a0
; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16
@@ -188,7 +188,7 @@ define i64 @caller_tiny_scalar_ret() nounwind {
; RV64I-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: addi s0, sp, 16
-; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret
+; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret at plt
; RV64I-WITHFP-NEXT: sext.w a0, a0
; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll b/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
index 4cad6819532a..59f825477b17 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
@@ -43,7 +43,7 @@ define float @caller_onstack_f32_noop(float %a) nounwind {
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: mv a7, zero
-; RV32IF-NEXT: call onstack_f32_noop
+; RV32IF-NEXT: call onstack_f32_noop at plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
@@ -70,7 +70,7 @@ define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: mv a7, zero
-; RV32IF-NEXT: call onstack_f32_noop
+; RV32IF-NEXT: call onstack_f32_noop at plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/stack-realignment.ll b/llvm/test/CodeGen/RISCV/stack-realignment.ll
index fb7e668e721f..6f72a2488c27 100644
--- a/llvm/test/CodeGen/RISCV/stack-realignment.ll
+++ b/llvm/test/CodeGen/RISCV/stack-realignment.ll
@@ -6,13 +6,17 @@
declare void @callee(i8*)
-define void @caller32() nounwind {
+define void @caller32() {
; RV32I-LABEL: caller32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: addi s0, sp, 32
+; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: andi sp, sp, -32
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
@@ -25,9 +29,13 @@ define void @caller32() nounwind {
; RV64I-LABEL: caller32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: addi s0, sp, 32
+; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: andi sp, sp, -32
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
@@ -41,11 +49,13 @@ define void @caller32() nounwind {
ret void
}
-define void @caller_no_realign32() nounwind "no-realign-stack" {
+define void @caller_no_realign32() "no-realign-stack" {
; RV32I-LABEL: caller_no_realign32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -55,7 +65,9 @@ define void @caller_no_realign32() nounwind "no-realign-stack" {
; RV64I-LABEL: caller_no_realign32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -66,13 +78,17 @@ define void @caller_no_realign32() nounwind "no-realign-stack" {
ret void
}
-define void @caller64() nounwind {
+define void @caller64() {
; RV32I-LABEL: caller64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -64
+; RV32I-NEXT: .cfi_def_cfa_offset 64
; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: addi s0, sp, 64
+; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: andi sp, sp, -64
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
@@ -85,9 +101,13 @@ define void @caller64() nounwind {
; RV64I-LABEL: caller64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64
+; RV64I-NEXT: .cfi_def_cfa_offset 64
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: addi s0, sp, 64
+; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: andi sp, sp, -64
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
@@ -101,11 +121,13 @@ define void @caller64() nounwind {
ret void
}
-define void @caller_no_realign64() nounwind "no-realign-stack" {
+define void @caller_no_realign64() "no-realign-stack" {
; RV32I-LABEL: caller_no_realign64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -115,7 +137,9 @@ define void @caller_no_realign64() nounwind "no-realign-stack" {
; RV64I-LABEL: caller_no_realign64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -126,13 +150,17 @@ define void @caller_no_realign64() nounwind "no-realign-stack" {
ret void
}
-define void @caller128() nounwind {
+define void @caller128() {
; RV32I-LABEL: caller128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -128
+; RV32I-NEXT: .cfi_def_cfa_offset 128
; RV32I-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: addi s0, sp, 128
+; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: andi sp, sp, -128
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
@@ -145,9 +173,13 @@ define void @caller128() nounwind {
; RV64I-LABEL: caller128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -128
+; RV64I-NEXT: .cfi_def_cfa_offset 128
; RV64I-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: addi s0, sp, 128
+; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: andi sp, sp, -128
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
@@ -161,11 +193,13 @@ define void @caller128() nounwind {
ret void
}
-define void @caller_no_realign128() nounwind "no-realign-stack" {
+define void @caller_no_realign128() "no-realign-stack" {
; RV32I-LABEL: caller_no_realign128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -175,7 +209,9 @@ define void @caller_no_realign128() nounwind "no-realign-stack" {
; RV64I-LABEL: caller_no_realign128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -186,13 +222,17 @@ define void @caller_no_realign128() nounwind "no-realign-stack" {
ret void
}
-define void @caller256() nounwind {
+define void @caller256() {
; RV32I-LABEL: caller256:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -256
+; RV32I-NEXT: .cfi_def_cfa_offset 256
; RV32I-NEXT: sw ra, 252(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: addi s0, sp, 256
+; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: andi sp, sp, -256
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
@@ -205,9 +245,13 @@ define void @caller256() nounwind {
; RV64I-LABEL: caller256:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -256
+; RV64I-NEXT: .cfi_def_cfa_offset 256
; RV64I-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: addi s0, sp, 256
+; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: andi sp, sp, -256
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
@@ -221,11 +265,13 @@ define void @caller256() nounwind {
ret void
}
-define void @caller_no_realign256() nounwind "no-realign-stack" {
+define void @caller_no_realign256() "no-realign-stack" {
; RV32I-LABEL: caller_no_realign256:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -235,7 +281,9 @@ define void @caller_no_realign256() nounwind "no-realign-stack" {
; RV64I-LABEL: caller_no_realign256:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -246,13 +294,17 @@ define void @caller_no_realign256() nounwind "no-realign-stack" {
ret void
}
-define void @caller512() nounwind {
+define void @caller512() {
; RV32I-LABEL: caller512:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -1024
+; RV32I-NEXT: .cfi_def_cfa_offset 1024
; RV32I-NEXT: sw ra, 1020(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 1016(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: addi s0, sp, 1024
+; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: andi sp, sp, -512
; RV32I-NEXT: addi a0, sp, 512
; RV32I-NEXT: call callee at plt
@@ -265,9 +317,13 @@ define void @caller512() nounwind {
; RV64I-LABEL: caller512:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -1024
+; RV64I-NEXT: .cfi_def_cfa_offset 1024
; RV64I-NEXT: sd ra, 1016(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 1008(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: addi s0, sp, 1024
+; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: andi sp, sp, -512
; RV64I-NEXT: addi a0, sp, 512
; RV64I-NEXT: call callee at plt
@@ -281,11 +337,13 @@ define void @caller512() nounwind {
ret void
}
-define void @caller_no_realign512() nounwind "no-realign-stack" {
+define void @caller_no_realign512() "no-realign-stack" {
; RV32I-LABEL: caller_no_realign512:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -295,7 +353,9 @@ define void @caller_no_realign512() nounwind "no-realign-stack" {
; RV64I-LABEL: caller_no_realign512:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -306,13 +366,17 @@ define void @caller_no_realign512() nounwind "no-realign-stack" {
ret void
}
-define void @caller1024() nounwind {
+define void @caller1024() {
; RV32I-LABEL: caller1024:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -2032
+; RV32I-NEXT: .cfi_def_cfa_offset 2032
; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: addi s0, sp, 2032
+; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: andi sp, sp, -1024
; RV32I-NEXT: addi a0, sp, 1024
@@ -327,9 +391,13 @@ define void @caller1024() nounwind {
; RV64I-LABEL: caller1024:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -2032
+; RV64I-NEXT: .cfi_def_cfa_offset 2032
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: addi s0, sp, 2032
+; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: andi sp, sp, -1024
; RV64I-NEXT: addi a0, sp, 1024
@@ -345,11 +413,13 @@ define void @caller1024() nounwind {
ret void
}
-define void @caller_no_realign1024() nounwind "no-realign-stack" {
+define void @caller_no_realign1024() "no-realign-stack" {
; RV32I-LABEL: caller_no_realign1024:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -359,7 +429,9 @@ define void @caller_no_realign1024() nounwind "no-realign-stack" {
; RV64I-LABEL: caller_no_realign1024:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -370,13 +442,17 @@ define void @caller_no_realign1024() nounwind "no-realign-stack" {
ret void
}
-define void @caller2048() nounwind {
+define void @caller2048() {
; RV32I-LABEL: caller2048:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -2032
+; RV32I-NEXT: .cfi_def_cfa_offset 2032
; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: addi s0, sp, 2032
+; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a0, a0, -2032
; RV32I-NEXT: sub sp, sp, a0
@@ -399,9 +475,13 @@ define void @caller2048() nounwind {
; RV64I-LABEL: caller2048:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -2032
+; RV64I-NEXT: .cfi_def_cfa_offset 2032
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: addi s0, sp, 2032
+; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, -2032
; RV64I-NEXT: sub sp, sp, a0
@@ -425,11 +505,13 @@ define void @caller2048() nounwind {
ret void
}
-define void @caller_no_realign2048() nounwind "no-realign-stack" {
+define void @caller_no_realign2048() "no-realign-stack" {
; RV32I-LABEL: caller_no_realign2048:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -439,7 +521,9 @@ define void @caller_no_realign2048() nounwind "no-realign-stack" {
; RV64I-LABEL: caller_no_realign2048:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -450,13 +534,17 @@ define void @caller_no_realign2048() nounwind "no-realign-stack" {
ret void
}
-define void @caller4096() nounwind {
+define void @caller4096() {
; RV32I-LABEL: caller4096:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -2032
+; RV32I-NEXT: .cfi_def_cfa_offset 2032
; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
+; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: addi s0, sp, 2032
+; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: lui a0, 2
; RV32I-NEXT: addi a0, a0, -2032
; RV32I-NEXT: sub sp, sp, a0
@@ -479,9 +567,13 @@ define void @caller4096() nounwind {
; RV64I-LABEL: caller4096:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -2032
+; RV64I-NEXT: .cfi_def_cfa_offset 2032
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
+; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: addi s0, sp, 2032
+; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: lui a0, 2
; RV64I-NEXT: addiw a0, a0, -2032
; RV64I-NEXT: sub sp, sp, a0
@@ -505,11 +597,13 @@ define void @caller4096() nounwind {
ret void
}
-define void @caller_no_realign4096() nounwind "no-realign-stack" {
+define void @caller_no_realign4096() "no-realign-stack" {
; RV32I-LABEL: caller_no_realign4096:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: mv a0, sp
; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -519,7 +613,9 @@ define void @caller_no_realign4096() nounwind "no-realign-stack" {
; RV64I-LABEL: caller_no_realign4096:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index 440f1b4a8547..7c50fa3883bb 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -429,7 +429,7 @@ define void @va1_caller() nounwind {
; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888
; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 2
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
-; ILP32-ILP32F-FPELIM-NEXT: call va1
+; ILP32-ILP32F-FPELIM-NEXT: call va1 at plt
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret
@@ -443,7 +443,7 @@ define void @va1_caller() nounwind {
; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888
; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 2
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
-; ILP32-ILP32F-WITHFP-NEXT: call va1
+; ILP32-ILP32F-WITHFP-NEXT: call va1 at plt
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
@@ -456,7 +456,7 @@ define void @va1_caller() nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 2
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va1 at plt
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
@@ -468,7 +468,7 @@ define void @va1_caller() nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1023
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, zero, 2
-; LP64-LP64F-LP64D-FPELIM-NEXT: call va1
+; LP64-LP64F-LP64D-FPELIM-NEXT: call va1 at plt
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
@@ -482,7 +482,7 @@ define void @va1_caller() nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1023
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, zero, 2
-; LP64-LP64F-LP64D-WITHFP-NEXT: call va1
+; LP64-LP64F-LP64D-WITHFP-NEXT: call va1 at plt
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16
@@ -754,7 +754,7 @@ define void @va2_caller() nounwind {
; ILP32-ILP32F-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; ILP32-ILP32F-FPELIM-NEXT: lui a3, 261888
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
-; ILP32-ILP32F-FPELIM-NEXT: call va2
+; ILP32-ILP32F-FPELIM-NEXT: call va2 at plt
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret
@@ -767,7 +767,7 @@ define void @va2_caller() nounwind {
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: lui a3, 261888
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
-; ILP32-ILP32F-WITHFP-NEXT: call va2
+; ILP32-ILP32F-WITHFP-NEXT: call va2 at plt
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
@@ -779,7 +779,7 @@ define void @va2_caller() nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a3, 261888
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va2 at plt
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
@@ -790,7 +790,7 @@ define void @va2_caller() nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 1023
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52
-; LP64-LP64F-LP64D-FPELIM-NEXT: call va2
+; LP64-LP64F-LP64D-FPELIM-NEXT: call va2 at plt
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
@@ -803,7 +803,7 @@ define void @va2_caller() nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 1023
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52
-; LP64-LP64F-LP64D-WITHFP-NEXT: call va2
+; LP64-LP64F-LP64D-WITHFP-NEXT: call va2 at plt
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16
@@ -1090,7 +1090,7 @@ define void @va3_caller() nounwind {
; ILP32-ILP32F-FPELIM-NEXT: lui a5, 262144
; ILP32-ILP32F-FPELIM-NEXT: mv a2, zero
; ILP32-ILP32F-FPELIM-NEXT: mv a4, zero
-; ILP32-ILP32F-FPELIM-NEXT: call va3
+; ILP32-ILP32F-FPELIM-NEXT: call va3 at plt
; ILP32-ILP32F-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 16
; ILP32-ILP32F-FPELIM-NEXT: ret
@@ -1106,7 +1106,7 @@ define void @va3_caller() nounwind {
; ILP32-ILP32F-WITHFP-NEXT: lui a5, 262144
; ILP32-ILP32F-WITHFP-NEXT: mv a2, zero
; ILP32-ILP32F-WITHFP-NEXT: mv a4, zero
-; ILP32-ILP32F-WITHFP-NEXT: call va3
+; ILP32-ILP32F-WITHFP-NEXT: call va3 at plt
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 16
@@ -1121,7 +1121,7 @@ define void @va3_caller() nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 262144
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a2, zero
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: mv a4, zero
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: call va3 at plt
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 16
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
@@ -1134,7 +1134,7 @@ define void @va3_caller() nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 62
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, zero, 2
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, zero, 1111
-; LP64-LP64F-LP64D-FPELIM-NEXT: call va3
+; LP64-LP64F-LP64D-FPELIM-NEXT: call va3 at plt
; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
@@ -1149,7 +1149,7 @@ define void @va3_caller() nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 62
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, zero, 2
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, zero, 1111
-; LP64-LP64F-LP64D-WITHFP-NEXT: call va3
+; LP64-LP64F-LP64D-WITHFP-NEXT: call va3 at plt
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 16
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