[llvm-branch-commits] [llvm] 09db958 - [RISCV] Improve scalable-vector shift tests (NFC)
Fraser Cormack via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Jan 12 03:51:22 PST 2021
Author: Fraser Cormack
Date: 2021-01-12T11:40:21Z
New Revision: 09db958e37b3a51942827a48a4b2f453e8fb4737
URL: https://github.com/llvm/llvm-project/commit/09db958e37b3a51942827a48a4b2f453e8fb4737
DIFF: https://github.com/llvm/llvm-project/commit/09db958e37b3a51942827a48a4b2f453e8fb4737.diff
LOG: [RISCV] Improve scalable-vector shift tests (NFC)
All i8/i16 and several i32 tests were testing immediate shift amounts
which exceeded the bits in the vector elements, creating poison values.
Amend the tests to test well-behaved shift amounts.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
index 34d055777cc3..b1490c8fb0f8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
@@ -17,22 +17,9 @@ define <vscale x 1 x i8> @vshl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
- %vc = shl <vscale x 1 x i8> %va, %splat
- ret <vscale x 1 x i8> %vc
-}
-
-define <vscale x 1 x i8> @vshl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv1i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 1 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = shl <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
@@ -54,22 +41,9 @@ define <vscale x 2 x i8> @vshl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
- %vc = shl <vscale x 2 x i8> %va, %splat
- ret <vscale x 2 x i8> %vc
-}
-
-define <vscale x 2 x i8> @vshl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv2i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 2 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = shl <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
@@ -91,22 +65,9 @@ define <vscale x 4 x i8> @vshl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
- %vc = shl <vscale x 4 x i8> %va, %splat
- ret <vscale x 4 x i8> %vc
-}
-
-define <vscale x 4 x i8> @vshl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv4i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = shl <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
@@ -128,22 +89,9 @@ define <vscale x 8 x i8> @vshl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
- %vc = shl <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i8> %vc
-}
-
-define <vscale x 8 x i8> @vshl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 8 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
@@ -165,22 +113,9 @@ define <vscale x 16 x i8> @vshl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %vc = shl <vscale x 16 x i8> %va, %splat
- ret <vscale x 16 x i8> %vc
-}
-
-define <vscale x 16 x i8> @vshl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv16i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 16 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = shl <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
@@ -202,22 +137,9 @@ define <vscale x 32 x i8> @vshl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
- %vc = shl <vscale x 32 x i8> %va, %splat
- ret <vscale x 32 x i8> %vc
-}
-
-define <vscale x 32 x i8> @vshl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv32i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 32 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = shl <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
@@ -239,22 +161,9 @@ define <vscale x 64 x i8> @vshl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
- %vc = shl <vscale x 64 x i8> %va, %splat
- ret <vscale x 64 x i8> %vc
-}
-
-define <vscale x 64 x i8> @vshl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv64i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 64 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = shl <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
@@ -276,22 +185,9 @@ define <vscale x 1 x i16> @vshl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
- %vc = shl <vscale x 1 x i16> %va, %splat
- ret <vscale x 1 x i16> %vc
-}
-
-define <vscale x 1 x i16> @vshl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv1i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 1 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = shl <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
@@ -313,22 +209,9 @@ define <vscale x 2 x i16> @vshl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
- %vc = shl <vscale x 2 x i16> %va, %splat
- ret <vscale x 2 x i16> %vc
-}
-
-define <vscale x 2 x i16> @vshl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv2i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 2 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = shl <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
@@ -350,22 +233,9 @@ define <vscale x 4 x i16> @vshl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
- %vc = shl <vscale x 4 x i16> %va, %splat
- ret <vscale x 4 x i16> %vc
-}
-
-define <vscale x 4 x i16> @vshl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv4i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 4 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = shl <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
@@ -387,22 +257,9 @@ define <vscale x 8 x i16> @vshl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %vc = shl <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i16> %vc
-}
-
-define <vscale x 8 x i16> @vshl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 8 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
@@ -424,22 +281,9 @@ define <vscale x 16 x i16> @vshl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
- %vc = shl <vscale x 16 x i16> %va, %splat
- ret <vscale x 16 x i16> %vc
-}
-
-define <vscale x 16 x i16> @vshl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv16i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 16 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = shl <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
@@ -461,22 +305,9 @@ define <vscale x 32 x i16> @vshl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
- %vc = shl <vscale x 32 x i16> %va, %splat
- ret <vscale x 32 x i16> %vc
-}
-
-define <vscale x 32 x i16> @vshl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv32i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 32 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = shl <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
@@ -506,19 +337,6 @@ define <vscale x 1 x i32> @vshl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %vc
}
-define <vscale x 1 x i32> @vshl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv1i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
- %vc = shl <vscale x 1 x i32> %va, %splat
- ret <vscale x 1 x i32> %vc
-}
-
define <vscale x 2 x i32> @vshl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vshl_vx_nxv2i32:
; CHECK: # %bb.0:
@@ -543,19 +361,6 @@ define <vscale x 2 x i32> @vshl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %vc
}
-define <vscale x 2 x i32> @vshl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv2i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
- %vc = shl <vscale x 2 x i32> %va, %splat
- ret <vscale x 2 x i32> %vc
-}
-
define <vscale x 4 x i32> @vshl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vshl_vx_nxv4i32:
; CHECK: # %bb.0:
@@ -580,19 +385,6 @@ define <vscale x 4 x i32> @vshl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %vc
}
-define <vscale x 4 x i32> @vshl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv4i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %vc = shl <vscale x 4 x i32> %va, %splat
- ret <vscale x 4 x i32> %vc
-}
-
define <vscale x 8 x i32> @vshl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vshl_vx_nxv8i32:
; CHECK: # %bb.0:
@@ -617,19 +409,6 @@ define <vscale x 8 x i32> @vshl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %vc
}
-define <vscale x 8 x i32> @vshl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
- %vc = shl <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i32> %vc
-}
-
define <vscale x 16 x i32> @vshl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
; CHECK-LABEL: vshl_vx_nxv16i32:
; CHECK: # %bb.0:
@@ -654,19 +433,6 @@ define <vscale x 16 x i32> @vshl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %vc
}
-define <vscale x 16 x i32> @vshl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv16i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
- %vc = shl <vscale x 16 x i32> %va, %splat
- ret <vscale x 16 x i32> %vc
-}
-
define <vscale x 1 x i64> @vshl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vshl_vx_nxv1i64:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
index 23c51934743f..5480f48f26ca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
@@ -17,22 +17,9 @@ define <vscale x 1 x i8> @vshl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
- %vc = shl <vscale x 1 x i8> %va, %splat
- ret <vscale x 1 x i8> %vc
-}
-
-define <vscale x 1 x i8> @vshl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv1i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 1 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = shl <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
@@ -54,22 +41,9 @@ define <vscale x 2 x i8> @vshl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
- %vc = shl <vscale x 2 x i8> %va, %splat
- ret <vscale x 2 x i8> %vc
-}
-
-define <vscale x 2 x i8> @vshl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv2i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 2 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = shl <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
@@ -91,22 +65,9 @@ define <vscale x 4 x i8> @vshl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
- %vc = shl <vscale x 4 x i8> %va, %splat
- ret <vscale x 4 x i8> %vc
-}
-
-define <vscale x 4 x i8> @vshl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv4i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = shl <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
@@ -128,22 +89,9 @@ define <vscale x 8 x i8> @vshl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
- %vc = shl <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i8> %vc
-}
-
-define <vscale x 8 x i8> @vshl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 8 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
@@ -165,22 +113,9 @@ define <vscale x 16 x i8> @vshl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %vc = shl <vscale x 16 x i8> %va, %splat
- ret <vscale x 16 x i8> %vc
-}
-
-define <vscale x 16 x i8> @vshl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv16i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 16 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = shl <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
@@ -202,22 +137,9 @@ define <vscale x 32 x i8> @vshl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
- %vc = shl <vscale x 32 x i8> %va, %splat
- ret <vscale x 32 x i8> %vc
-}
-
-define <vscale x 32 x i8> @vshl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv32i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 32 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = shl <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
@@ -239,22 +161,9 @@ define <vscale x 64 x i8> @vshl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vshl_vx_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
- %vc = shl <vscale x 64 x i8> %va, %splat
- ret <vscale x 64 x i8> %vc
-}
-
-define <vscale x 64 x i8> @vshl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
-; CHECK-LABEL: vshl_vx_nxv64i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 64 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = shl <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
@@ -276,22 +185,9 @@ define <vscale x 1 x i16> @vshl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
- %vc = shl <vscale x 1 x i16> %va, %splat
- ret <vscale x 1 x i16> %vc
-}
-
-define <vscale x 1 x i16> @vshl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv1i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 1 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = shl <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
@@ -313,22 +209,9 @@ define <vscale x 2 x i16> @vshl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
- %vc = shl <vscale x 2 x i16> %va, %splat
- ret <vscale x 2 x i16> %vc
-}
-
-define <vscale x 2 x i16> @vshl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv2i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 2 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = shl <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
@@ -350,22 +233,9 @@ define <vscale x 4 x i16> @vshl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
- %vc = shl <vscale x 4 x i16> %va, %splat
- ret <vscale x 4 x i16> %vc
-}
-
-define <vscale x 4 x i16> @vshl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv4i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 4 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = shl <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
@@ -387,22 +257,9 @@ define <vscale x 8 x i16> @vshl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %vc = shl <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i16> %vc
-}
-
-define <vscale x 8 x i16> @vshl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 8 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
@@ -424,22 +281,9 @@ define <vscale x 16 x i16> @vshl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
- %vc = shl <vscale x 16 x i16> %va, %splat
- ret <vscale x 16 x i16> %vc
-}
-
-define <vscale x 16 x i16> @vshl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv16i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 16 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = shl <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
@@ -461,22 +305,9 @@ define <vscale x 32 x i16> @vshl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vshl_vx_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsll.vi v16, v16, 31
+; CHECK-NEXT: vsll.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
- %vc = shl <vscale x 32 x i16> %va, %splat
- ret <vscale x 32 x i16> %vc
-}
-
-define <vscale x 32 x i16> @vshl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: vshl_vx_nxv32i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 32 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = shl <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
@@ -506,19 +337,6 @@ define <vscale x 1 x i32> @vshl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %vc
}
-define <vscale x 1 x i32> @vshl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv1i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
- %vc = shl <vscale x 1 x i32> %va, %splat
- ret <vscale x 1 x i32> %vc
-}
-
define <vscale x 2 x i32> @vshl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vshl_vx_nxv2i32:
; CHECK: # %bb.0:
@@ -543,19 +361,6 @@ define <vscale x 2 x i32> @vshl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %vc
}
-define <vscale x 2 x i32> @vshl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv2i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
- %vc = shl <vscale x 2 x i32> %va, %splat
- ret <vscale x 2 x i32> %vc
-}
-
define <vscale x 4 x i32> @vshl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vshl_vx_nxv4i32:
; CHECK: # %bb.0:
@@ -580,19 +385,6 @@ define <vscale x 4 x i32> @vshl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %vc
}
-define <vscale x 4 x i32> @vshl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv4i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %vc = shl <vscale x 4 x i32> %va, %splat
- ret <vscale x 4 x i32> %vc
-}
-
define <vscale x 8 x i32> @vshl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vshl_vx_nxv8i32:
; CHECK: # %bb.0:
@@ -617,19 +409,6 @@ define <vscale x 8 x i32> @vshl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %vc
}
-define <vscale x 8 x i32> @vshl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
- %vc = shl <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i32> %vc
-}
-
define <vscale x 16 x i32> @vshl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vshl_vx_nxv16i32:
; CHECK: # %bb.0:
@@ -654,19 +433,6 @@ define <vscale x 16 x i32> @vshl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %vc
}
-define <vscale x 16 x i32> @vshl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
-; CHECK-LABEL: vshl_vx_nxv16i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vsll.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
- %vc = shl <vscale x 16 x i32> %va, %splat
- ret <vscale x 16 x i32> %vc
-}
-
define <vscale x 1 x i64> @vshl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vshl_vx_nxv1i64:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
index ed5ca9025f84..3d8a203a94c8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
@@ -27,22 +27,9 @@ define <vscale x 1 x i8> @vsra_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
- %vc = ashr <vscale x 1 x i8> %va, %splat
- ret <vscale x 1 x i8> %vc
-}
-
-define <vscale x 1 x i8> @vsra_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv1i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 1 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = ashr <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
@@ -74,22 +61,9 @@ define <vscale x 2 x i8> @vsra_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
- %vc = ashr <vscale x 2 x i8> %va, %splat
- ret <vscale x 2 x i8> %vc
-}
-
-define <vscale x 2 x i8> @vsra_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv2i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 2 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = ashr <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
@@ -121,22 +95,9 @@ define <vscale x 4 x i8> @vsra_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
- %vc = ashr <vscale x 4 x i8> %va, %splat
- ret <vscale x 4 x i8> %vc
-}
-
-define <vscale x 4 x i8> @vsra_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv4i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = ashr <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
@@ -168,22 +129,9 @@ define <vscale x 8 x i8> @vsra_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
- %vc = ashr <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i8> %vc
-}
-
-define <vscale x 8 x i8> @vsra_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 8 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
@@ -215,22 +163,9 @@ define <vscale x 16 x i8> @vsra_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %vc = ashr <vscale x 16 x i8> %va, %splat
- ret <vscale x 16 x i8> %vc
-}
-
-define <vscale x 16 x i8> @vsra_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv16i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 16 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = ashr <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
@@ -262,22 +197,9 @@ define <vscale x 32 x i8> @vsra_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
- %vc = ashr <vscale x 32 x i8> %va, %splat
- ret <vscale x 32 x i8> %vc
-}
-
-define <vscale x 32 x i8> @vsra_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv32i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 32 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = ashr <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
@@ -310,22 +232,9 @@ define <vscale x 64 x i8> @vsra_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
- %vc = ashr <vscale x 64 x i8> %va, %splat
- ret <vscale x 64 x i8> %vc
-}
-
-define <vscale x 64 x i8> @vsra_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv64i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 64 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = ashr <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
@@ -357,22 +266,9 @@ define <vscale x 1 x i16> @vsra_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
- %vc = ashr <vscale x 1 x i16> %va, %splat
- ret <vscale x 1 x i16> %vc
-}
-
-define <vscale x 1 x i16> @vsra_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv1i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 1 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = ashr <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
@@ -404,22 +300,9 @@ define <vscale x 2 x i16> @vsra_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
- %vc = ashr <vscale x 2 x i16> %va, %splat
- ret <vscale x 2 x i16> %vc
-}
-
-define <vscale x 2 x i16> @vsra_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv2i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 2 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = ashr <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
@@ -451,22 +334,9 @@ define <vscale x 4 x i16> @vsra_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
- %vc = ashr <vscale x 4 x i16> %va, %splat
- ret <vscale x 4 x i16> %vc
-}
-
-define <vscale x 4 x i16> @vsra_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv4i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 4 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = ashr <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
@@ -498,22 +368,9 @@ define <vscale x 8 x i16> @vsra_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %vc = ashr <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i16> %vc
-}
-
-define <vscale x 8 x i16> @vsra_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 8 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
@@ -545,22 +402,9 @@ define <vscale x 16 x i16> @vsra_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
- %vc = ashr <vscale x 16 x i16> %va, %splat
- ret <vscale x 16 x i16> %vc
-}
-
-define <vscale x 16 x i16> @vsra_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv16i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 16 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = ashr <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
@@ -593,22 +437,9 @@ define <vscale x 32 x i16> @vsra_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
- %vc = ashr <vscale x 32 x i16> %va, %splat
- ret <vscale x 32 x i16> %vc
-}
-
-define <vscale x 32 x i16> @vsra_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv32i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 32 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = ashr <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
@@ -648,19 +479,6 @@ define <vscale x 1 x i32> @vsra_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %vc
}
-define <vscale x 1 x i32> @vsra_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv1i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
- %vc = ashr <vscale x 1 x i32> %va, %splat
- ret <vscale x 1 x i32> %vc
-}
-
define <vscale x 2 x i32> @vsra_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vsra_vv_nxv2i32:
; CHECK: # %bb.0:
@@ -695,19 +513,6 @@ define <vscale x 2 x i32> @vsra_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %vc
}
-define <vscale x 2 x i32> @vsra_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv2i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
- %vc = ashr <vscale x 2 x i32> %va, %splat
- ret <vscale x 2 x i32> %vc
-}
-
define <vscale x 4 x i32> @vsra_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vsra_vv_nxv4i32:
; CHECK: # %bb.0:
@@ -742,19 +547,6 @@ define <vscale x 4 x i32> @vsra_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %vc
}
-define <vscale x 4 x i32> @vsra_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv4i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %vc = ashr <vscale x 4 x i32> %va, %splat
- ret <vscale x 4 x i32> %vc
-}
-
define <vscale x 8 x i32> @vsra_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vsra_vv_nxv8i32:
; CHECK: # %bb.0:
@@ -789,19 +581,6 @@ define <vscale x 8 x i32> @vsra_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %vc
}
-define <vscale x 8 x i32> @vsra_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
- %vc = ashr <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i32> %vc
-}
-
define <vscale x 16 x i32> @vsra_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vsra_vv_nxv16i32:
; CHECK: # %bb.0:
@@ -837,19 +616,6 @@ define <vscale x 16 x i32> @vsra_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %vc
}
-define <vscale x 16 x i32> @vsra_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv16i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
- %vc = ashr <vscale x 16 x i32> %va, %splat
- ret <vscale x 16 x i32> %vc
-}
-
define <vscale x 1 x i64> @vsra_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vsra_vv_nxv1i64:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
index 550dcb579485..68f5ba2cf620 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
@@ -27,22 +27,9 @@ define <vscale x 1 x i8> @vsra_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
- %vc = ashr <vscale x 1 x i8> %va, %splat
- ret <vscale x 1 x i8> %vc
-}
-
-define <vscale x 1 x i8> @vsra_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv1i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 1 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = ashr <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
@@ -74,22 +61,9 @@ define <vscale x 2 x i8> @vsra_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
- %vc = ashr <vscale x 2 x i8> %va, %splat
- ret <vscale x 2 x i8> %vc
-}
-
-define <vscale x 2 x i8> @vsra_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv2i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 2 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = ashr <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
@@ -121,22 +95,9 @@ define <vscale x 4 x i8> @vsra_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
- %vc = ashr <vscale x 4 x i8> %va, %splat
- ret <vscale x 4 x i8> %vc
-}
-
-define <vscale x 4 x i8> @vsra_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv4i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = ashr <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
@@ -168,22 +129,9 @@ define <vscale x 8 x i8> @vsra_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
- %vc = ashr <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i8> %vc
-}
-
-define <vscale x 8 x i8> @vsra_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 8 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
@@ -215,22 +163,9 @@ define <vscale x 16 x i8> @vsra_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %vc = ashr <vscale x 16 x i8> %va, %splat
- ret <vscale x 16 x i8> %vc
-}
-
-define <vscale x 16 x i8> @vsra_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv16i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 16 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = ashr <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
@@ -262,22 +197,9 @@ define <vscale x 32 x i8> @vsra_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
- %vc = ashr <vscale x 32 x i8> %va, %splat
- ret <vscale x 32 x i8> %vc
-}
-
-define <vscale x 32 x i8> @vsra_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv32i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 32 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = ashr <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
@@ -310,22 +232,9 @@ define <vscale x 64 x i8> @vsra_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vsra_vi_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
- %vc = ashr <vscale x 64 x i8> %va, %splat
- ret <vscale x 64 x i8> %vc
-}
-
-define <vscale x 64 x i8> @vsra_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
-; CHECK-LABEL: vsra_vi_nxv64i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 64 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = ashr <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
@@ -357,22 +266,9 @@ define <vscale x 1 x i16> @vsra_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
- %vc = ashr <vscale x 1 x i16> %va, %splat
- ret <vscale x 1 x i16> %vc
-}
-
-define <vscale x 1 x i16> @vsra_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv1i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 1 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = ashr <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
@@ -404,22 +300,9 @@ define <vscale x 2 x i16> @vsra_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
- %vc = ashr <vscale x 2 x i16> %va, %splat
- ret <vscale x 2 x i16> %vc
-}
-
-define <vscale x 2 x i16> @vsra_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv2i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 2 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = ashr <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
@@ -451,22 +334,9 @@ define <vscale x 4 x i16> @vsra_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
- %vc = ashr <vscale x 4 x i16> %va, %splat
- ret <vscale x 4 x i16> %vc
-}
-
-define <vscale x 4 x i16> @vsra_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv4i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 4 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = ashr <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
@@ -498,22 +368,9 @@ define <vscale x 8 x i16> @vsra_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %vc = ashr <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i16> %vc
-}
-
-define <vscale x 8 x i16> @vsra_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 8 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
@@ -545,22 +402,9 @@ define <vscale x 16 x i16> @vsra_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
- %vc = ashr <vscale x 16 x i16> %va, %splat
- ret <vscale x 16 x i16> %vc
-}
-
-define <vscale x 16 x i16> @vsra_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv16i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 16 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = ashr <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
@@ -593,22 +437,9 @@ define <vscale x 32 x i16> @vsra_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vsra_vi_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
- %vc = ashr <vscale x 32 x i16> %va, %splat
- ret <vscale x 32 x i16> %vc
-}
-
-define <vscale x 32 x i16> @vsra_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: vsra_vi_nxv32i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 32 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = ashr <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
@@ -648,19 +479,6 @@ define <vscale x 1 x i32> @vsra_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %vc
}
-define <vscale x 1 x i32> @vsra_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv1i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
- %vc = ashr <vscale x 1 x i32> %va, %splat
- ret <vscale x 1 x i32> %vc
-}
-
define <vscale x 2 x i32> @vsra_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vsra_vv_nxv2i32:
; CHECK: # %bb.0:
@@ -695,19 +513,6 @@ define <vscale x 2 x i32> @vsra_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %vc
}
-define <vscale x 2 x i32> @vsra_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv2i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
- %vc = ashr <vscale x 2 x i32> %va, %splat
- ret <vscale x 2 x i32> %vc
-}
-
define <vscale x 4 x i32> @vsra_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vsra_vv_nxv4i32:
; CHECK: # %bb.0:
@@ -742,19 +547,6 @@ define <vscale x 4 x i32> @vsra_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %vc
}
-define <vscale x 4 x i32> @vsra_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv4i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %vc = ashr <vscale x 4 x i32> %va, %splat
- ret <vscale x 4 x i32> %vc
-}
-
define <vscale x 8 x i32> @vsra_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vsra_vv_nxv8i32:
; CHECK: # %bb.0:
@@ -789,19 +581,6 @@ define <vscale x 8 x i32> @vsra_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %vc
}
-define <vscale x 8 x i32> @vsra_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
- %vc = ashr <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i32> %vc
-}
-
define <vscale x 16 x i32> @vsra_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-LABEL: vsra_vv_nxv16i32:
; CHECK: # %bb.0:
@@ -837,19 +616,6 @@ define <vscale x 16 x i32> @vsra_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %vc
}
-define <vscale x 16 x i32> @vsra_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
-; CHECK-LABEL: vsra_vi_nxv16i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vsra.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
- %vc = ashr <vscale x 16 x i32> %va, %splat
- ret <vscale x 16 x i32> %vc
-}
-
define <vscale x 1 x i64> @vsra_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-LABEL: vsra_vv_nxv1i64:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
index 7d0b1af014de..448c4f2ba93e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
@@ -17,22 +17,9 @@ define <vscale x 1 x i8> @vsrl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
- %vc = lshr <vscale x 1 x i8> %va, %splat
- ret <vscale x 1 x i8> %vc
-}
-
-define <vscale x 1 x i8> @vsrl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv1i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 1 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
@@ -54,22 +41,9 @@ define <vscale x 2 x i8> @vsrl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
- %vc = lshr <vscale x 2 x i8> %va, %splat
- ret <vscale x 2 x i8> %vc
-}
-
-define <vscale x 2 x i8> @vsrl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv2i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 2 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
@@ -91,22 +65,9 @@ define <vscale x 4 x i8> @vsrl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
- %vc = lshr <vscale x 4 x i8> %va, %splat
- ret <vscale x 4 x i8> %vc
-}
-
-define <vscale x 4 x i8> @vsrl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv4i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
@@ -128,22 +89,9 @@ define <vscale x 8 x i8> @vsrl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
- %vc = lshr <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i8> %vc
-}
-
-define <vscale x 8 x i8> @vsrl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 8 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
@@ -165,22 +113,9 @@ define <vscale x 16 x i8> @vsrl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %vc = lshr <vscale x 16 x i8> %va, %splat
- ret <vscale x 16 x i8> %vc
-}
-
-define <vscale x 16 x i8> @vsrl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv16i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 16 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
@@ -202,22 +137,9 @@ define <vscale x 32 x i8> @vsrl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
- %vc = lshr <vscale x 32 x i8> %va, %splat
- ret <vscale x 32 x i8> %vc
-}
-
-define <vscale x 32 x i8> @vsrl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv32i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 32 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = lshr <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
@@ -239,22 +161,9 @@ define <vscale x 64 x i8> @vsrl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
- %vc = lshr <vscale x 64 x i8> %va, %splat
- ret <vscale x 64 x i8> %vc
-}
-
-define <vscale x 64 x i8> @vsrl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv64i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 64 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = lshr <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
@@ -276,22 +185,9 @@ define <vscale x 1 x i16> @vsrl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
- %vc = lshr <vscale x 1 x i16> %va, %splat
- ret <vscale x 1 x i16> %vc
-}
-
-define <vscale x 1 x i16> @vsrl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv1i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 1 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
@@ -313,22 +209,9 @@ define <vscale x 2 x i16> @vsrl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
- %vc = lshr <vscale x 2 x i16> %va, %splat
- ret <vscale x 2 x i16> %vc
-}
-
-define <vscale x 2 x i16> @vsrl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv2i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 2 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
@@ -350,22 +233,9 @@ define <vscale x 4 x i16> @vsrl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
- %vc = lshr <vscale x 4 x i16> %va, %splat
- ret <vscale x 4 x i16> %vc
-}
-
-define <vscale x 4 x i16> @vsrl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv4i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 4 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
@@ -387,22 +257,9 @@ define <vscale x 8 x i16> @vsrl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %vc = lshr <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i16> %vc
-}
-
-define <vscale x 8 x i16> @vsrl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 8 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
@@ -424,22 +281,9 @@ define <vscale x 16 x i16> @vsrl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
- %vc = lshr <vscale x 16 x i16> %va, %splat
- ret <vscale x 16 x i16> %vc
-}
-
-define <vscale x 16 x i16> @vsrl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv16i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 16 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
@@ -461,22 +305,9 @@ define <vscale x 32 x i16> @vsrl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
- %vc = lshr <vscale x 32 x i16> %va, %splat
- ret <vscale x 32 x i16> %vc
-}
-
-define <vscale x 32 x i16> @vsrl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv32i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 32 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = lshr <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
@@ -506,19 +337,6 @@ define <vscale x 1 x i32> @vsrl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %vc
}
-define <vscale x 1 x i32> @vsrl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv1i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
- %vc = lshr <vscale x 1 x i32> %va, %splat
- ret <vscale x 1 x i32> %vc
-}
-
define <vscale x 2 x i32> @vsrl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vsrl_vx_nxv2i32:
; CHECK: # %bb.0:
@@ -543,19 +361,6 @@ define <vscale x 2 x i32> @vsrl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %vc
}
-define <vscale x 2 x i32> @vsrl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv2i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
- %vc = lshr <vscale x 2 x i32> %va, %splat
- ret <vscale x 2 x i32> %vc
-}
-
define <vscale x 4 x i32> @vsrl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vsrl_vx_nxv4i32:
; CHECK: # %bb.0:
@@ -580,19 +385,6 @@ define <vscale x 4 x i32> @vsrl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %vc
}
-define <vscale x 4 x i32> @vsrl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv4i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %vc = lshr <vscale x 4 x i32> %va, %splat
- ret <vscale x 4 x i32> %vc
-}
-
define <vscale x 8 x i32> @vsrl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vsrl_vx_nxv8i32:
; CHECK: # %bb.0:
@@ -617,19 +409,6 @@ define <vscale x 8 x i32> @vsrl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %vc
}
-define <vscale x 8 x i32> @vsrl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
- %vc = lshr <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i32> %vc
-}
-
define <vscale x 16 x i32> @vsrl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
; CHECK-LABEL: vsrl_vx_nxv16i32:
; CHECK: # %bb.0:
@@ -654,19 +433,6 @@ define <vscale x 16 x i32> @vsrl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %vc
}
-define <vscale x 16 x i32> @vsrl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv16i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
- %vc = lshr <vscale x 16 x i32> %va, %splat
- ret <vscale x 16 x i32> %vc
-}
-
define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vsrl_vx_nxv1i64:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
index d1aa31746f8b..0a5157d95523 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
@@ -17,22 +17,9 @@ define <vscale x 1 x i8> @vsrl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
- %vc = lshr <vscale x 1 x i8> %va, %splat
- ret <vscale x 1 x i8> %vc
-}
-
-define <vscale x 1 x i8> @vsrl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv1i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 1 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
@@ -54,22 +41,9 @@ define <vscale x 2 x i8> @vsrl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
- %vc = lshr <vscale x 2 x i8> %va, %splat
- ret <vscale x 2 x i8> %vc
-}
-
-define <vscale x 2 x i8> @vsrl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv2i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 2 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
@@ -91,22 +65,9 @@ define <vscale x 4 x i8> @vsrl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
- %vc = lshr <vscale x 4 x i8> %va, %splat
- ret <vscale x 4 x i8> %vc
-}
-
-define <vscale x 4 x i8> @vsrl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv4i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
@@ -128,22 +89,9 @@ define <vscale x 8 x i8> @vsrl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
- %vc = lshr <vscale x 8 x i8> %va, %splat
- ret <vscale x 8 x i8> %vc
-}
-
-define <vscale x 8 x i8> @vsrl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv8i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 8 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
@@ -165,22 +113,9 @@ define <vscale x 16 x i8> @vsrl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
- %vc = lshr <vscale x 16 x i8> %va, %splat
- ret <vscale x 16 x i8> %vc
-}
-
-define <vscale x 16 x i8> @vsrl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv16i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 16 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
@@ -202,22 +137,9 @@ define <vscale x 32 x i8> @vsrl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
- %vc = lshr <vscale x 32 x i8> %va, %splat
- ret <vscale x 32 x i8> %vc
-}
-
-define <vscale x 32 x i8> @vsrl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv32i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 32 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = lshr <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
@@ -239,22 +161,9 @@ define <vscale x 64 x i8> @vsrl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
- %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
- %vc = lshr <vscale x 64 x i8> %va, %splat
- ret <vscale x 64 x i8> %vc
-}
-
-define <vscale x 64 x i8> @vsrl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
-; CHECK-LABEL: vsrl_vx_nxv64i8_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+ %head = insertelement <vscale x 64 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = lshr <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
@@ -276,22 +185,9 @@ define <vscale x 1 x i16> @vsrl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
- %vc = lshr <vscale x 1 x i16> %va, %splat
- ret <vscale x 1 x i16> %vc
-}
-
-define <vscale x 1 x i16> @vsrl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv1i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 1 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
@@ -313,22 +209,9 @@ define <vscale x 2 x i16> @vsrl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
- %vc = lshr <vscale x 2 x i16> %va, %splat
- ret <vscale x 2 x i16> %vc
-}
-
-define <vscale x 2 x i16> @vsrl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv2i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 2 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
@@ -350,22 +233,9 @@ define <vscale x 4 x i16> @vsrl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
- %vc = lshr <vscale x 4 x i16> %va, %splat
- ret <vscale x 4 x i16> %vc
-}
-
-define <vscale x 4 x i16> @vsrl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv4i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 4 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
@@ -387,22 +257,9 @@ define <vscale x 8 x i16> @vsrl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
- %vc = lshr <vscale x 8 x i16> %va, %splat
- ret <vscale x 8 x i16> %vc
-}
-
-define <vscale x 8 x i16> @vsrl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv8i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 8 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
@@ -424,22 +281,9 @@ define <vscale x 16 x i16> @vsrl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
- %vc = lshr <vscale x 16 x i16> %va, %splat
- ret <vscale x 16 x i16> %vc
-}
-
-define <vscale x 16 x i16> @vsrl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv16i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 16 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
@@ -461,22 +305,9 @@ define <vscale x 32 x i16> @vsrl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsrl.vi v16, v16, 31
+; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
- %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
- %vc = lshr <vscale x 32 x i16> %va, %splat
- ret <vscale x 32 x i16> %vc
-}
-
-define <vscale x 32 x i16> @vsrl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
-; CHECK-LABEL: vsrl_vx_nxv32i16_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+ %head = insertelement <vscale x 32 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = lshr <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
@@ -506,19 +337,6 @@ define <vscale x 1 x i32> @vsrl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %vc
}
-define <vscale x 1 x i32> @vsrl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv1i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
- %vc = lshr <vscale x 1 x i32> %va, %splat
- ret <vscale x 1 x i32> %vc
-}
-
define <vscale x 2 x i32> @vsrl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vsrl_vx_nxv2i32:
; CHECK: # %bb.0:
@@ -543,19 +361,6 @@ define <vscale x 2 x i32> @vsrl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %vc
}
-define <vscale x 2 x i32> @vsrl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv2i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
- %vc = lshr <vscale x 2 x i32> %va, %splat
- ret <vscale x 2 x i32> %vc
-}
-
define <vscale x 4 x i32> @vsrl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vsrl_vx_nxv4i32:
; CHECK: # %bb.0:
@@ -580,19 +385,6 @@ define <vscale x 4 x i32> @vsrl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %vc
}
-define <vscale x 4 x i32> @vsrl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv4i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
- %vc = lshr <vscale x 4 x i32> %va, %splat
- ret <vscale x 4 x i32> %vc
-}
-
define <vscale x 8 x i32> @vsrl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vsrl_vx_nxv8i32:
; CHECK: # %bb.0:
@@ -617,19 +409,6 @@ define <vscale x 8 x i32> @vsrl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %vc
}
-define <vscale x 8 x i32> @vsrl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv8i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
- %vc = lshr <vscale x 8 x i32> %va, %splat
- ret <vscale x 8 x i32> %vc
-}
-
define <vscale x 16 x i32> @vsrl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vsrl_vx_nxv16i32:
; CHECK: # %bb.0:
@@ -654,19 +433,6 @@ define <vscale x 16 x i32> @vsrl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %vc
}
-define <vscale x 16 x i32> @vsrl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
-; CHECK-LABEL: vsrl_vx_nxv16i32_1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, zero, 32
-; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vsrl.vx v16, v16, a0
-; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
- %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
- %vc = lshr <vscale x 16 x i32> %va, %splat
- ret <vscale x 16 x i32> %vc
-}
-
define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vsrl_vx_nxv1i64:
; CHECK: # %bb.0:
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