[llvm-branch-commits] [llvm] 7b9f541 - [X86][SSE] Add tests for unpack(hop(), hop())
Simon Pilgrim via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jan 8 06:17:13 PST 2021
Author: Simon Pilgrim
Date: 2021-01-08T14:11:37Z
New Revision: 7b9f541c1edb24a676508906cfbcaaf228cc6a2e
URL: https://github.com/llvm/llvm-project/commit/7b9f541c1edb24a676508906cfbcaaf228cc6a2e
DIFF: https://github.com/llvm/llvm-project/commit/7b9f541c1edb24a676508906cfbcaaf228cc6a2e.diff
LOG: [X86][SSE] Add tests for unpack(hop(),hop())
We should be able to convert these to permute(hop()) as we only ever use one of the ops from each hop.
Added:
llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll b/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
new file mode 100644
index 000000000000..7acd85604800
--- /dev/null
+++ b/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s
+
+;
+; 128-bit Vectors
+;
+
+define <4 x float> @test_unpacklo_hadd_v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) {
+; CHECK-LABEL: test_unpacklo_hadd_v4f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vhaddps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vhaddps %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: ret{{[l|q]}}
+ %5 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %0, <4 x float> %1) #4
+ %6 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x float> %3) #4
+ %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ ret <4 x float> %7
+}
+
+define <4 x float> @test_unpackhi_hadd_v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) {
+; CHECK-LABEL: test_unpackhi_hadd_v4f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vhaddps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vhaddps %xmm3, %xmm0, %xmm1
+; CHECK-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: ret{{[l|q]}}
+ %5 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %0, <4 x float> %1) #4
+ %6 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x float> %3) #4
+ %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ ret <4 x float> %7
+}
+
+define <4 x float> @test_unpacklo_hsub_v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) {
+; CHECK-LABEL: test_unpacklo_hsub_v4f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vhsubps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vhsubps %xmm0, %xmm2, %xmm1
+; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: ret{{[l|q]}}
+ %5 = tail call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %0, <4 x float> %1) #4
+ %6 = tail call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %2, <4 x float> %3) #4
+ %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ ret <4 x float> %7
+}
+
+define <4 x float> @test_unpackhi_hsub_v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) {
+; CHECK-LABEL: test_unpackhi_hsub_v4f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vhsubps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vhsubps %xmm3, %xmm0, %xmm1
+; CHECK-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: ret{{[l|q]}}
+ %5 = tail call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %0, <4 x float> %1) #4
+ %6 = tail call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %2, <4 x float> %3) #4
+ %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ ret <4 x float> %7
+}
+
+;
+; 256-bit Vectors
+;
+
+define <8 x float> @test_unpacklo_hadd_v8f32(<8 x float> %0, <8 x float> %1, <8 x float> %2, <8 x float> %3) {
+; CHECK-LABEL: test_unpacklo_hadd_v8f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vhaddps %ymm0, %ymm0, %ymm0
+; CHECK-NEXT: vhaddps %ymm0, %ymm2, %ymm1
+; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
+; CHECK-NEXT: ret{{[l|q]}}
+ %5 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %0, <8 x float> %1) #4
+ %6 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %2, <8 x float> %3) #4
+ %7 = shufflevector <8 x float> %5, <8 x float> %6, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
+ ret <8 x float> %7
+}
+
+define <8 x float> @test_unpackhi_hadd_v8f32(<8 x float> %0, <8 x float> %1, <8 x float> %2, <8 x float> %3) {
+; CHECK-LABEL: test_unpackhi_hadd_v8f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vhaddps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vhaddps %ymm3, %ymm0, %ymm1
+; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
+; CHECK-NEXT: ret{{[l|q]}}
+ %5 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %0, <8 x float> %1) #4
+ %6 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %2, <8 x float> %3) #4
+ %7 = shufflevector <8 x float> %5, <8 x float> %6, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
+ ret <8 x float> %7
+}
+
+define <8 x float> @test_unpacklo_hsub_v8f32(<8 x float> %0, <8 x float> %1, <8 x float> %2, <8 x float> %3) {
+; CHECK-LABEL: test_unpacklo_hsub_v8f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vhsubps %ymm0, %ymm0, %ymm0
+; CHECK-NEXT: vhsubps %ymm0, %ymm2, %ymm1
+; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
+; CHECK-NEXT: ret{{[l|q]}}
+ %5 = tail call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %0, <8 x float> %1) #4
+ %6 = tail call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %2, <8 x float> %3) #4
+ %7 = shufflevector <8 x float> %5, <8 x float> %6, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
+ ret <8 x float> %7
+}
+
+define <8 x float> @test_unpackhi_hsub_v8f32(<8 x float> %0, <8 x float> %1, <8 x float> %2, <8 x float> %3) {
+; CHECK-LABEL: test_unpackhi_hsub_v8f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vhsubps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vhsubps %ymm3, %ymm0, %ymm1
+; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
+; CHECK-NEXT: ret{{[l|q]}}
+ %5 = tail call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %0, <8 x float> %1) #4
+ %6 = tail call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %2, <8 x float> %3) #4
+ %7 = shufflevector <8 x float> %5, <8 x float> %6, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
+ ret <8 x float> %7
+}
+
+declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
+
+declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>)
+declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>)
+
+declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
+
+declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>)
+declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>)
+declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>)
+declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>)
+
+declare <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16>, <16 x i16>)
+declare <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32>, <8 x i32>)
+declare <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16>, <16 x i16>)
+declare <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32>, <8 x i32>)
+
+declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>)
+declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>)
+declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>)
+declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>)
More information about the llvm-branch-commits
mailing list