[llvm-branch-commits] [llvm] c68faed - [RISCV] Return a vXi1 vector type from getSetCCResultType if V extension is enabled.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-06T11:50:15-08:00
New Revision: c68faed041e664be5b289eae00ee4ca855ddf1c9

URL: https://github.com/llvm/llvm-project/commit/c68faed041e664be5b289eae00ee4ca855ddf1c9
DIFF: https://github.com/llvm/llvm-project/commit/c68faed041e664be5b289eae00ee4ca855ddf1c9.diff

LOG: [RISCV] Return a vXi1 vector type from getSetCCResultType if V extension is enabled.

nvxXi1 types are legal with V extension and that's the result
vmseq/vmsne/vmslt/etc instructions return.

No test cases yet because the setcc isel patterns aren't in
and we'll need more than basic tests to observe this. I locally
tested that this plus D947078, D94168, D94142, and D94149
was enough to be able to handle the overflow result from
llvm.sadd.overflow.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a097df996ad2..ba6548e48303 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -398,6 +398,8 @@ EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
                                             EVT VT) const {
   if (!VT.isVector())
     return getPointerTy(DL);
+  if (Subtarget.hasStdExtV())
+    return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
   return VT.changeVectorElementTypeToInteger();
 }