[llvm-branch-commits] [llvm] e8cdcae - [X86] Accept 64-bit GPRs for vextractps when using a register that requires EVEX.

[Tom Stellard via llvm-branch-commits]

Author: Craig Topper
Date: 2021-02-03T19:41:57-08:00
New Revision: e8cdcaeae406527c9a76b3dc5c522391c81dfdfd

URL: https://github.com/llvm/llvm-project/commit/e8cdcaeae406527c9a76b3dc5c522391c81dfdfd
DIFF: https://github.com/llvm/llvm-project/commit/e8cdcaeae406527c9a76b3dc5c522391c81dfdfd.diff

LOG: [X86] Accept 64-bit GPRs for vextractps when using a register that requires EVEX.

This is consistent with the VEX version. It also fixes a sorting
issue in the matching table that caused the EVEX version to be
prioritized over VEX in intel syntax.

Fixes issue [2] from PR48991.

(cherry picked from commit c691fe14da93a7c9eff466231515d6d4d16124fa)

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrAVX512.td
    llvm/test/MC/X86/intel-syntax-x86-64-avx.s
    llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 0c2b278fdd7b..19012797ae9a 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -1123,10 +1123,10 @@ defm : vextract_for_mask_cast<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
                               EXTRACT_get_vextract256_imm, [HasAVX512]>;
 
 // vextractps - extract 32 bits from XMM
-def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
+def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32orGR64:$dst),
       (ins VR128X:$src1, u8imm:$src2),
       "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-      [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
+      [(set GR32orGR64:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
       EVEX, VEX_WIG, Sched<[WriteVecExtract]>;
 
 def VEXTRACTPSZmr : AVX512AIi8<0x17, MRMDestMem, (outs),

diff  --git a/llvm/test/MC/X86/intel-syntax-x86-64-avx.s b/llvm/test/MC/X86/intel-syntax-x86-64-avx.s
index bb57cb287f38..c1f20d204a8c 100644
--- a/llvm/test/MC/X86/intel-syntax-x86-64-avx.s
+++ b/llvm/test/MC/X86/intel-syntax-x86-64-avx.s
@@ -167,3 +167,7 @@
 // CHECK: vpmaddwd ymm1, ymm2, ymmword ptr [rcx + 8*r14 - 536870910]
 // CHECK: encoding: [0xc4,0xa1,0x6d,0xf5,0x8c,0xf1,0x02,0x00,0x00,0xe0]
           vpmaddwd ymm1, ymm2, ymmword ptr [rcx + 8*r14 - 536870910]
+
+// CHECK: vextractps ecx, xmm2, 1
+// CHECK: encoding: [0xc4,0xe3,0x79,0x17,0xd1,0x01]
+          vextractps ecx, xmm2, 1

diff  --git a/llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s b/llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
index 29bde03c5860..31c43afe5017 100644
--- a/llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
+++ b/llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
@@ -1260,3 +1260,6 @@
 // CHECK: encoding: [0x62,0xf1,0x7e,0x89,0xe6,0x11]
           vcvtdq2pd xmm2 {k1} {z}, qword ptr [rcx]
 
+// CHECK: vextractps ecx, xmm17, 1
+// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x17,0xc9,0x01]
+          vextractps rcx, xmm17, 1