[llvm-branch-commits] [llvm] 40659cd - [RISCV] Rename RISCVGenSystemOperands.inc to RISCVGenSearchableTables.inc to prepare for more tables. NFC

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-11-30T20:47:58-08:00
New Revision: 40659cd2c6f4347650d477a16e0cf60ce4401fa6

URL: https://github.com/llvm/llvm-project/commit/40659cd2c6f4347650d477a16e0cf60ce4401fa6
DIFF: https://github.com/llvm/llvm-project/commit/40659cd2c6f4347650d477a16e0cf60ce4401fa6.diff

LOG: [RISCV] Rename RISCVGenSystemOperands.inc to RISCVGenSearchableTables.inc to prepare for more tables. NFC

D89449 adds more tables so renaming as a pre-commit for that.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/CMakeLists.txt
    llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
    llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index f0dce3bc8d85..8996eed153eb 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -13,8 +13,8 @@ tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM RISCVGenSystemOperands.inc -gen-searchable-tables)
 
 add_public_tablegen_target(RISCVCommonTableGen)
 

diff  --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
index 89a975d705ff..cc170d9f34ca 100644
--- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
@@ -19,7 +19,7 @@
 namespace llvm {
 namespace RISCVSysReg {
 #define GET_SysRegsList_IMPL
-#include "RISCVGenSystemOperands.inc"
+#include "RISCVGenSearchableTables.inc"
 } // namespace RISCVSysReg
 
 namespace RISCVABI {

diff  --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
index 0affca31880f..3043cd777dc2 100644
--- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -236,7 +236,7 @@ struct SysReg {
 };
 
 #define GET_SysRegsList_DECL
-#include "RISCVGenSystemOperands.inc"
+#include "RISCVGenSearchableTables.inc"
 } // end namespace RISCVSysReg
 
 namespace RISCVABI {