[llvm-branch-commits] [llvm] 44a679e - [VE] Change the behaviour of truncate
Kazushi Marukawa via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Nov 30 05:17:35 PST 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-11-30T22:12:45+09:00
New Revision: 44a679eaa40cf234c79c241012607ed5f7bada77
URL: https://github.com/llvm/llvm-project/commit/44a679eaa40cf234c79c241012607ed5f7bada77
DIFF: https://github.com/llvm/llvm-project/commit/44a679eaa40cf234c79c241012607ed5f7bada77.diff
LOG: [VE] Change the behaviour of truncate
Change the way to truncate i64 to i32 in I64 registers. VE assumed
sext values previously. Change it to zext values this time to make
it match to the LLVM behaviour.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92226
Added:
Modified:
llvm/lib/Target/VE/VEInstrInfo.td
llvm/test/CodeGen/VE/Scalar/br_jt.ll
llvm/test/CodeGen/VE/Scalar/select.ll
llvm/test/CodeGen/VE/Scalar/select_cc.ll
llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll
llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
llvm/test/CodeGen/VE/VELIntrinsics/vbrd.ll
llvm/test/CodeGen/VE/Vector/vec_add.ll
llvm/test/CodeGen/VE/Vector/vec_broadcast.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 86635adf9ef2..5837267aa63b 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -1656,7 +1656,7 @@ def : Pat<(i32 (and (trunc i64:$src), 0xffff)),
// Cast to i32
def : Pat<(i32 (trunc i64:$src)),
- (ADDSWSXrm (EXTRACT_SUBREG $src, sub_i32), 0)>;
+ (EXTRACT_SUBREG (ANDrm $src, !add(32, 64)), sub_i32)>;
def : Pat<(i32 (fp_to_sint f32:$src)), (CVTWSSXr RD_RZ, $src)>;
def : Pat<(i32 (fp_to_sint f64:$src)), (CVTWDSXr RD_RZ, $src)>;
def : Pat<(i32 (fp_to_sint f128:$src)), (CVTWDSXr RD_RZ, (CVTDQr $src))>;
diff --git a/llvm/test/CodeGen/VE/Scalar/br_jt.ll b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
index d84e830299ff..88d5378830a1 100644
--- a/llvm/test/CodeGen/VE/Scalar/br_jt.ll
+++ b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
@@ -10,7 +10,7 @@
define signext i32 @br_jt3(i32 signext %0) {
; CHECK-LABEL: br_jt3:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: breq.w 4, %s0, .LBB{{[0-9]+}}_5
@@ -32,7 +32,7 @@ define signext i32 @br_jt3(i32 signext %0) {
;
; PIC-LABEL: br_jt3:
; PIC: # %bb.0:
-; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: breq.w 1, %s0, .LBB0_1
; PIC-NEXT: # %bb.2:
; PIC-NEXT: breq.w 4, %s0, .LBB0_5
@@ -75,7 +75,7 @@ define signext i32 @br_jt3(i32 signext %0) {
define signext i32 @br_jt4(i32 signext %0) {
; CHECK-LABEL: br_jt4:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: cmpu.w %s2, 3, %s1
; CHECK-NEXT: brgt.w 0, %s2, .LBB{{[0-9]+}}_2
@@ -93,7 +93,7 @@ define signext i32 @br_jt4(i32 signext %0) {
;
; PIC-LABEL: br_jt4:
; PIC: .LBB{{[0-9]+}}_5:
-; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: adds.w.sx %s1, -1, %s0
; PIC-NEXT: cmpu.w %s2, 3, %s1
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_ at pc_lo(-24)
@@ -131,7 +131,7 @@ define signext i32 @br_jt4(i32 signext %0) {
define signext i32 @br_jt7(i32 signext %0) {
; CHECK-LABEL: br_jt7:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: cmpu.w %s2, 8, %s1
; CHECK-NEXT: brgt.w 0, %s2, .LBB{{[0-9]+}}_3
@@ -156,7 +156,7 @@ define signext i32 @br_jt7(i32 signext %0) {
;
; PIC-LABEL: br_jt7:
; PIC: .LBB{{[0-9]+}}_6:
-; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: adds.w.sx %s1, -1, %s0
; PIC-NEXT: cmpu.w %s2, 8, %s1
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_ at pc_lo(-24)
@@ -208,7 +208,7 @@ define signext i32 @br_jt7(i32 signext %0) {
define signext i32 @br_jt8(i32 signext %0) {
; CHECK-LABEL: br_jt8:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: cmpu.w %s2, 8, %s1
; CHECK-NEXT: brgt.w 0, %s2, .LBB{{[0-9]+}}_3
@@ -233,7 +233,7 @@ define signext i32 @br_jt8(i32 signext %0) {
;
; PIC-LABEL: br_jt8:
; PIC: .LBB{{[0-9]+}}_6:
-; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: adds.w.sx %s1, -1, %s0
; PIC-NEXT: cmpu.w %s2, 8, %s1
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_ at pc_lo(-24)
@@ -285,7 +285,7 @@ define signext i32 @br_jt8(i32 signext %0) {
define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: br_jt3_m:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: breq.w 4, %s0, .LBB{{[0-9]+}}_5
@@ -300,7 +300,7 @@ define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: and %s0, %s1, (32)0
; CHECK-NEXT: adds.w.sx %s0, 3, %s0
; CHECK-NEXT: .LBB{{[0-9]+}}_6:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
@@ -308,7 +308,7 @@ define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
;
; PIC-LABEL: br_jt3_m:
; PIC: # %bb.0:
-; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: breq.w 1, %s0, .LBB4_1
; PIC-NEXT: # %bb.2:
; PIC-NEXT: breq.w 4, %s0, .LBB4_5
@@ -323,7 +323,7 @@ define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
; PIC-NEXT: b.l.t (, %s10)
; PIC-NEXT: .LBB4_5:
-; PIC-NEXT: adds.w.sx %s0, %s1, (0)1
+; PIC-NEXT: and %s0, %s1, (32)0
; PIC-NEXT: adds.w.sx %s0, 3, %s0
; PIC-NEXT: .LBB4_6:
; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
@@ -353,7 +353,7 @@ define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
define signext i32 @br_jt4_m(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: br_jt4_m:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: adds.w.sx %s2, -1, %s0
; CHECK-NEXT: cmpu.w %s3, 3, %s2
; CHECK-NEXT: brgt.w 0, %s3, .LBB{{[0-9]+}}_5
@@ -375,7 +375,7 @@ define signext i32 @br_jt4_m(i32 signext %0, i32 signext %1) {
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_4:
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: and %s0, %s1, (32)0
; CHECK-NEXT: adds.w.sx %s0, 3, %s0
; CHECK-NEXT: .LBB{{[0-9]+}}_5:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
@@ -383,7 +383,7 @@ define signext i32 @br_jt4_m(i32 signext %0, i32 signext %1) {
;
; PIC-LABEL: br_jt4_m:
; PIC: # %bb.0:
-; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: brlt.w 2, %s0, .LBB5_4
; PIC-NEXT: # %bb.1:
; PIC-NEXT: breq.w 1, %s0, .LBB5_8
@@ -398,7 +398,7 @@ define signext i32 @br_jt4_m(i32 signext %0, i32 signext %1) {
; PIC-NEXT: # %bb.5:
; PIC-NEXT: brne.w 4, %s0, .LBB5_7
; PIC-NEXT: # %bb.6:
-; PIC-NEXT: adds.w.sx %s0, %s1, (0)1
+; PIC-NEXT: and %s0, %s1, (32)0
; PIC-NEXT: adds.w.sx %s0, 3, %s0
; PIC-NEXT: .LBB5_7:
; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
@@ -440,7 +440,7 @@ define signext i32 @br_jt4_m(i32 signext %0, i32 signext %1) {
define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: br_jt7_m:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
+; CHECK-NEXT: and %s2, %s0, (32)0
; CHECK-NEXT: adds.w.sx %s0, -1, %s2
; CHECK-NEXT: cmpu.w %s3, 8, %s0
; CHECK-NEXT: brgt.w 0, %s3, .LBB{{[0-9]+}}_8
@@ -451,7 +451,7 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) {
; CHECK-NEXT: and %s3, %s3, (32)0
; CHECK-NEXT: lea.sl %s3, .LJTI6_0 at hi(, %s3)
; CHECK-NEXT: ld %s3, (%s3, %s0)
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: b.l.t (, %s3)
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
@@ -486,12 +486,12 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) {
;
; PIC-LABEL: br_jt7_m:
; PIC: # %bb.0:
-; PIC-NEXT: adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: brge.w 3, %s0, .LBB6_1
; PIC-NEXT: # %bb.6:
; PIC-NEXT: brlt.w 7, %s0, .LBB6_10
; PIC-NEXT: # %bb.7:
-; PIC-NEXT: adds.w.sx %s1, %s1, (0)1
+; PIC-NEXT: and %s1, %s1, (32)0
; PIC-NEXT: breq.w 4, %s0, .LBB6_14
; PIC-NEXT: # %bb.8:
; PIC-NEXT: brne.w 7, %s0, .LBB6_16
@@ -576,7 +576,7 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) {
define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: br_jt8_m:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
+; CHECK-NEXT: and %s2, %s0, (32)0
; CHECK-NEXT: adds.w.sx %s0, -1, %s2
; CHECK-NEXT: cmpu.w %s3, 8, %s0
; CHECK-NEXT: brgt.w 0, %s3, .LBB{{[0-9]+}}_9
@@ -587,7 +587,7 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
; CHECK-NEXT: and %s3, %s3, (32)0
; CHECK-NEXT: lea.sl %s3, .LJTI7_0 at hi(, %s3)
; CHECK-NEXT: ld %s3, (%s3, %s0)
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: b.l.t (, %s3)
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
@@ -626,7 +626,7 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
;
; PIC-LABEL: br_jt8_m:
; PIC: .LBB{{[0-9]+}}_12:
-; PIC-NEXT: adds.w.sx %s2, %s0, (0)1
+; PIC-NEXT: and %s2, %s0, (32)0
; PIC-NEXT: adds.w.sx %s0, -1, %s2
; PIC-NEXT: cmpu.w %s3, 8, %s0
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_ at pc_lo(-24)
@@ -635,7 +635,7 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_ at pc_hi(%s16, %s15)
; PIC-NEXT: brgt.w 0, %s3, .LBB7_9
; PIC-NEXT: # %bb.1:
-; PIC-NEXT: adds.w.sx %s1, %s1, (0)1
+; PIC-NEXT: and %s1, %s1, (32)0
; PIC-NEXT: adds.w.zx %s0, %s0, (0)1
; PIC-NEXT: sll %s0, %s0, 2
; PIC-NEXT: lea %s3, .LJTI7_0 at gotoff_lo
diff --git a/llvm/test/CodeGen/VE/Scalar/select.ll b/llvm/test/CodeGen/VE/Scalar/select.ll
index 263358bde854..eeb3f036b7dc 100644
--- a/llvm/test/CodeGen/VE/Scalar/select.ll
+++ b/llvm/test/CodeGen/VE/Scalar/select.ll
@@ -119,7 +119,7 @@ define zeroext i32 @select_u32_var(i1 zeroext %0, i32 zeroext %1, i32 zeroext %2
define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) {
; CHECK-LABEL: select_i64_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
@@ -131,7 +131,7 @@ define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) {
define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) {
; CHECK-LABEL: select_u64_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
@@ -143,7 +143,7 @@ define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) {
define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) {
; CHECK-LABEL: select_i128_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -157,7 +157,7 @@ define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) {
define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) {
; CHECK-LABEL: select_u128_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -171,7 +171,7 @@ define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) {
define float @select_float_var(i1 zeroext %0, float %1, float %2) {
; CHECK-LABEL: select_float_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
@@ -183,7 +183,7 @@ define float @select_float_var(i1 zeroext %0, float %1, float %2) {
define double @select_double_var(i1 zeroext %0, double %1, double %2) {
; CHECK-LABEL: select_double_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
@@ -195,7 +195,7 @@ define double @select_double_var(i1 zeroext %0, double %1, double %2) {
define fp128 @select_quad_var(i1 zeroext %0, fp128 %1, fp128 %2) {
; CHECK-LABEL: select_quad_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
@@ -285,7 +285,7 @@ define zeroext i32 @select_u32_mimm(i1 zeroext %0, i32 zeroext %1) {
define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_i64_mimm:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -297,7 +297,7 @@ define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) {
define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_u64_mimm:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -309,7 +309,7 @@ define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) {
define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_i128_mimm:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
@@ -323,7 +323,7 @@ define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) {
define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_u128_mimm:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
@@ -337,7 +337,7 @@ define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) {
define float @select_float_mimm(i1 zeroext %0, float %1) {
; CHECK-LABEL: select_float_mimm:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -349,7 +349,7 @@ define float @select_float_mimm(i1 zeroext %0, float %1) {
define double @select_double_mimm(i1 zeroext %0, double %1) {
; CHECK-LABEL: select_double_mimm:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -366,7 +366,7 @@ define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) {
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0 at hi(, %s1)
; CHECK-NEXT: ld %s4, 8(, %s1)
; CHECK-NEXT: ld %s5, (, %s1)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2
@@ -458,7 +458,7 @@ define zeroext i32 @select_mimm_u32(i1 zeroext %0, i32 zeroext %1) {
define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_mimm_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -470,7 +470,7 @@ define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) {
define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_mimm_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -482,7 +482,7 @@ define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) {
define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_mimm_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
@@ -496,7 +496,7 @@ define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) {
define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_mimm_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
@@ -510,7 +510,7 @@ define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) {
define float @select_mimm_float(i1 zeroext %0, float %1) {
; CHECK-LABEL: select_mimm_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -522,7 +522,7 @@ define float @select_mimm_float(i1 zeroext %0, float %1) {
define double @select_mimm_double(i1 zeroext %0, double %1) {
; CHECK-LABEL: select_mimm_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -539,7 +539,7 @@ define fp128 @select_mimm_quad(i1 zeroext %0, fp128 %1) {
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0 at hi(, %s1)
; CHECK-NEXT: ld %s4, 8(, %s1)
; CHECK-NEXT: ld %s5, (, %s1)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
diff --git a/llvm/test/CodeGen/VE/Scalar/select_cc.ll b/llvm/test/CodeGen/VE/Scalar/select_cc.ll
index ba6c1c6ef28f..86c17bc798d4 100644
--- a/llvm/test/CodeGen/VE/Scalar/select_cc.ll
+++ b/llvm/test/CodeGen/VE/Scalar/select_cc.ll
@@ -1326,7 +1326,7 @@ define i64 @select_cc_i1_i64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i1_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
@@ -1515,7 +1515,7 @@ define i64 @select_cc_i1_u64(i1 zeroext %0, i1 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i1_u64:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
@@ -1704,7 +1704,7 @@ define i128 @select_cc_i1_i128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i1_i128:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2
@@ -1921,7 +1921,7 @@ define i128 @select_cc_i1_u128(i1 zeroext %0, i1 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i1_u128:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2
@@ -2138,7 +2138,7 @@ define float @select_cc_i1_float(i1 zeroext %0, i1 zeroext %1, float %2, float %
; CHECK-LABEL: select_cc_i1_float:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
@@ -2327,7 +2327,7 @@ define double @select_cc_i1_double(i1 zeroext %0, i1 zeroext %1, double %2, doub
; CHECK-LABEL: select_cc_i1_double:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
@@ -2516,7 +2516,7 @@ define fp128 @select_cc_i1_quad(i1 zeroext %0, i1 zeroext %1, fp128 %2, fp128 %3
; CHECK-LABEL: select_cc_i1_quad:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll b/llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll
index 507045b6b93c..17a9775d4474 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll
@@ -12,7 +12,7 @@ define void @lsv_vvss(i8* %0, i64 %1, i32 signext %2) {
; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld %v0, 8, %s0
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lsv %v0(%s2), %s1
; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: b.l.t (, %s10)
@@ -38,7 +38,7 @@ define i64 @lvsl_vssl_imm(i8* readonly %0, i32 signext %1) {
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: and %s0, %s1, (32)0
; CHECK-NEXT: lvs %s0, %v0(%s0)
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
@@ -56,7 +56,7 @@ define double @lvsd_vssl_imm(i8* readonly %0, i32 signext %1) {
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: and %s0, %s1, (32)0
; CHECK-NEXT: lvs %s0, %v0(%s0)
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
@@ -74,7 +74,7 @@ define float @lvss_vssl_imm(i8* readonly %0, i32 signext %1) {
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: and %s0, %s1, (32)0
; CHECK-NEXT: lvs %s0, %v0(%s0)
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll b/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
index 3b833d41ff3e..ac889e7b60ca 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
@@ -16,13 +16,13 @@ define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) {
; CHECK-NEXT: lea %s4, 256
; CHECK-NEXT: lvl %s4
; CHECK-NEXT: vld %v0, 8, %s2
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vst %v0, 16, %s3
; CHECK-NEXT: lea %s4, 128
; CHECK-NEXT: lvl %s4
; CHECK-NEXT: vld %v0, 16, %s2
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vst %v0, 16, %s3
; CHECK-NEXT: lvl %s4
@@ -47,7 +47,7 @@ define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) {
define void @stable_vl(i32 %evl, i8* %P, i8* %Q) {
; CHECK-LABEL: stable_vl:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vld %v0, 8, %s1
; CHECK-NEXT: vst %v0, 16, %s2
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vbrd.ll b/llvm/test/CodeGen/VE/VELIntrinsics/vbrd.ll
index 21dc9b6c8498..faba6f8c5222 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/vbrd.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vbrd.ll
@@ -263,7 +263,7 @@ declare <256 x double> @llvm.ve.vl.vbrds.vsmvl(float, <256 x i1>, <256 x double>
define void @vbrdw_vsl(i32 signext %0, i8* %1) {
; CHECK-LABEL: vbrdw_vsl:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vbrdl %v0, %s0
@@ -286,7 +286,7 @@ define void @vbrdw_vsvl(i32 signext %0, i8* %1) {
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: vbrdl %v0, %s0
; CHECK-NEXT: vst %v0, 8, %s1
; CHECK-NEXT: b.l.t (, %s10)
@@ -306,7 +306,7 @@ define void @vbrdw_vsmvl(i32 signext %0, i8* %1) {
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s1
-; CHECK-NEXT: adds.w.sx %s3, %s0, (0)1
+; CHECK-NEXT: and %s3, %s0, (32)0
; CHECK-NEXT: lvm %vm1, 3, %s0
; CHECK-NEXT: vbrdl %v0, %s3, %vm1
; CHECK-NEXT: vst %v0, 8, %s1
diff --git a/llvm/test/CodeGen/VE/Vector/vec_add.ll b/llvm/test/CodeGen/VE/Vector/vec_add.ll
index 74421332daab..18fbd61a8186 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_add.ll
@@ -5,11 +5,11 @@
; Function Attrs: nounwind
define fastcc <256 x i32> @add_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: add_vv_v256i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s0, 256
-; CHECK-NEXT: lvl %s0
-; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1
+; CHECK-NEXT: b.l.t (, %s10)
%z = add <256 x i32> %x, %y
ret <256 x i32> %z
}
@@ -17,12 +17,12 @@ define fastcc <256 x i32> @add_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; Function Attrs: nounwind
define fastcc <256 x i32> @add_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: add_sv_v256i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: lea %s1, 256
-; CHECK-NEXT: lvl %s1
-; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: lea %s1, 256
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0
+; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = add <256 x i32> %vx, %y
@@ -32,12 +32,12 @@ define fastcc <256 x i32> @add_sv_v256i32(i32 %x, <256 x i32> %y) {
; Function Attrs: nounwind
define fastcc <256 x i32> @add_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: add_vs_v256i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: lea %s1, 256
-; CHECK-NEXT: lvl %s1
-; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: lea %s1, 256
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0
+; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = add <256 x i32> %x, %vy
@@ -51,11 +51,11 @@ define fastcc <256 x i32> @add_vs_v256i32(<256 x i32> %x, i32 %y) {
; Function Attrs: nounwind
define fastcc <256 x i64> @add_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: add_vv_v256i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s0, 256
-; CHECK-NEXT: lvl %s0
-; CHECK-NEXT: vadds.l %v0, %v0, %v1
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: vadds.l %v0, %v0, %v1
+; CHECK-NEXT: b.l.t (, %s10)
%z = add <256 x i64> %x, %y
ret <256 x i64> %z
}
@@ -63,11 +63,11 @@ define fastcc <256 x i64> @add_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; Function Attrs: nounwind
define fastcc <256 x i64> @add_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: add_sv_v256i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 256
-; CHECK-NEXT: lvl %s1
-; CHECK-NEXT: vadds.l %v0, %s0, %v0
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s1, 256
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: vadds.l %v0, %s0, %v0
+; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = add <256 x i64> %vx, %y
@@ -77,11 +77,11 @@ define fastcc <256 x i64> @add_sv_v256i64(i64 %x, <256 x i64> %y) {
; Function Attrs: nounwind
define fastcc <256 x i64> @add_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: add_vs_v256i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 256
-; CHECK-NEXT: lvl %s1
-; CHECK-NEXT: vadds.l %v0, %s0, %v0
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s1, 256
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: vadds.l %v0, %s0, %v0
+; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = add <256 x i64> %x, %vy
@@ -94,11 +94,11 @@ define fastcc <256 x i64> @add_vs_v256i64(<256 x i64> %x, i64 %y) {
; Function Attrs: nounwind
define fastcc <128 x i64> @add_vv_v128i64(<128 x i64> %x, <128 x i64> %y) {
; CHECK-LABEL: add_vv_v128i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s0, 256
-; CHECK-NEXT: lvl %s0
-; CHECK-NEXT: vadds.l %v0, %v0, %v1
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: vadds.l %v0, %v0, %v1
+; CHECK-NEXT: b.l.t (, %s10)
%z = add <128 x i64> %x, %y
ret <128 x i64> %z
}
@@ -109,11 +109,11 @@ define fastcc <128 x i64> @add_vv_v128i64(<128 x i64> %x, <128 x i64> %y) {
; Function Attrs: nounwind
define fastcc <256 x i16> @add_vv_v256i16(<256 x i16> %x, <256 x i16> %y) {
; CHECK-LABEL: add_vv_v256i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s0, 256
-; CHECK-NEXT: lvl %s0
-; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1
+; CHECK-NEXT: b.l.t (, %s10)
%z = add <256 x i16> %x, %y
ret <256 x i16> %z
}
@@ -124,8 +124,7 @@ define fastcc <256 x i16> @add_vv_v256i16(<256 x i16> %x, <256 x i16> %y) {
; Function Attrs: nounwind
define fastcc <128 x i16> @add_vv_v128i16(<128 x i16> %x, <128 x i16> %y) {
; CHECK-LABEL: add_vv_v128i16:
-; CHECK: # %bb.0:
-; CHECK-NOT: vadd
+; CHECK-NOT: vadd
%z = add <128 x i16> %x, %y
ret <128 x i16> %z
}
diff --git a/llvm/test/CodeGen/VE/Vector/vec_broadcast.ll b/llvm/test/CodeGen/VE/Vector/vec_broadcast.ll
index 0445da22e83f..9422495bb892 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_broadcast.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_broadcast.ll
@@ -52,7 +52,7 @@ define fastcc <256 x double> @brdi_v256f64() {
define fastcc <256 x i32> @brd_v256i32(i32 %s) {
; CHECK-LABEL: brd_v256i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v0, %s0
@@ -127,7 +127,7 @@ define fastcc <128 x double> @brd_v128f64(double %s) {
define fastcc <128 x i32> @brd_v128i32(i32 %s) {
; CHECK-LABEL: brd_v128i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v0, %s0
@@ -177,7 +177,7 @@ define fastcc <128 x float> @brdi_v128f32(float %s) {
define fastcc <256 x i16> @brd_v256i16(i16 %s) {
; CHECK-LABEL: brd_v256i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v0, %s0
@@ -192,136 +192,136 @@ define fastcc <256 x i16> @brd_v256i16(i16 %s) {
define fastcc <128 x i16> @brd_v128i16(i16 %s) {
; CHECK-LABEL: brd_v128i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: st2b %s1, 254(, %s0)
-; CHECK-NEXT: st2b %s1, 252(, %s0)
-; CHECK-NEXT: st2b %s1, 250(, %s0)
-; CHECK-NEXT: st2b %s1, 248(, %s0)
-; CHECK-NEXT: st2b %s1, 246(, %s0)
-; CHECK-NEXT: st2b %s1, 244(, %s0)
-; CHECK-NEXT: st2b %s1, 242(, %s0)
-; CHECK-NEXT: st2b %s1, 240(, %s0)
-; CHECK-NEXT: st2b %s1, 238(, %s0)
-; CHECK-NEXT: st2b %s1, 236(, %s0)
-; CHECK-NEXT: st2b %s1, 234(, %s0)
-; CHECK-NEXT: st2b %s1, 232(, %s0)
-; CHECK-NEXT: st2b %s1, 230(, %s0)
-; CHECK-NEXT: st2b %s1, 228(, %s0)
-; CHECK-NEXT: st2b %s1, 226(, %s0)
-; CHECK-NEXT: st2b %s1, 224(, %s0)
-; CHECK-NEXT: st2b %s1, 222(, %s0)
-; CHECK-NEXT: st2b %s1, 220(, %s0)
-; CHECK-NEXT: st2b %s1, 218(, %s0)
-; CHECK-NEXT: st2b %s1, 216(, %s0)
-; CHECK-NEXT: st2b %s1, 214(, %s0)
-; CHECK-NEXT: st2b %s1, 212(, %s0)
-; CHECK-NEXT: st2b %s1, 210(, %s0)
-; CHECK-NEXT: st2b %s1, 208(, %s0)
-; CHECK-NEXT: st2b %s1, 206(, %s0)
-; CHECK-NEXT: st2b %s1, 204(, %s0)
-; CHECK-NEXT: st2b %s1, 202(, %s0)
-; CHECK-NEXT: st2b %s1, 200(, %s0)
-; CHECK-NEXT: st2b %s1, 198(, %s0)
-; CHECK-NEXT: st2b %s1, 196(, %s0)
-; CHECK-NEXT: st2b %s1, 194(, %s0)
-; CHECK-NEXT: st2b %s1, 192(, %s0)
-; CHECK-NEXT: st2b %s1, 190(, %s0)
-; CHECK-NEXT: st2b %s1, 188(, %s0)
-; CHECK-NEXT: st2b %s1, 186(, %s0)
-; CHECK-NEXT: st2b %s1, 184(, %s0)
-; CHECK-NEXT: st2b %s1, 182(, %s0)
-; CHECK-NEXT: st2b %s1, 180(, %s0)
-; CHECK-NEXT: st2b %s1, 178(, %s0)
-; CHECK-NEXT: st2b %s1, 176(, %s0)
-; CHECK-NEXT: st2b %s1, 174(, %s0)
-; CHECK-NEXT: st2b %s1, 172(, %s0)
-; CHECK-NEXT: st2b %s1, 170(, %s0)
-; CHECK-NEXT: st2b %s1, 168(, %s0)
-; CHECK-NEXT: st2b %s1, 166(, %s0)
-; CHECK-NEXT: st2b %s1, 164(, %s0)
-; CHECK-NEXT: st2b %s1, 162(, %s0)
-; CHECK-NEXT: st2b %s1, 160(, %s0)
-; CHECK-NEXT: st2b %s1, 158(, %s0)
-; CHECK-NEXT: st2b %s1, 156(, %s0)
-; CHECK-NEXT: st2b %s1, 154(, %s0)
-; CHECK-NEXT: st2b %s1, 152(, %s0)
-; CHECK-NEXT: st2b %s1, 150(, %s0)
-; CHECK-NEXT: st2b %s1, 148(, %s0)
-; CHECK-NEXT: st2b %s1, 146(, %s0)
-; CHECK-NEXT: st2b %s1, 144(, %s0)
-; CHECK-NEXT: st2b %s1, 142(, %s0)
-; CHECK-NEXT: st2b %s1, 140(, %s0)
-; CHECK-NEXT: st2b %s1, 138(, %s0)
-; CHECK-NEXT: st2b %s1, 136(, %s0)
-; CHECK-NEXT: st2b %s1, 134(, %s0)
-; CHECK-NEXT: st2b %s1, 132(, %s0)
-; CHECK-NEXT: st2b %s1, 130(, %s0)
-; CHECK-NEXT: st2b %s1, 128(, %s0)
-; CHECK-NEXT: st2b %s1, 126(, %s0)
-; CHECK-NEXT: st2b %s1, 124(, %s0)
-; CHECK-NEXT: st2b %s1, 122(, %s0)
-; CHECK-NEXT: st2b %s1, 120(, %s0)
-; CHECK-NEXT: st2b %s1, 118(, %s0)
-; CHECK-NEXT: st2b %s1, 116(, %s0)
-; CHECK-NEXT: st2b %s1, 114(, %s0)
-; CHECK-NEXT: st2b %s1, 112(, %s0)
-; CHECK-NEXT: st2b %s1, 110(, %s0)
-; CHECK-NEXT: st2b %s1, 108(, %s0)
-; CHECK-NEXT: st2b %s1, 106(, %s0)
-; CHECK-NEXT: st2b %s1, 104(, %s0)
-; CHECK-NEXT: st2b %s1, 102(, %s0)
-; CHECK-NEXT: st2b %s1, 100(, %s0)
-; CHECK-NEXT: st2b %s1, 98(, %s0)
-; CHECK-NEXT: st2b %s1, 96(, %s0)
-; CHECK-NEXT: st2b %s1, 94(, %s0)
-; CHECK-NEXT: st2b %s1, 92(, %s0)
-; CHECK-NEXT: st2b %s1, 90(, %s0)
-; CHECK-NEXT: st2b %s1, 88(, %s0)
-; CHECK-NEXT: st2b %s1, 86(, %s0)
-; CHECK-NEXT: st2b %s1, 84(, %s0)
-; CHECK-NEXT: st2b %s1, 82(, %s0)
-; CHECK-NEXT: st2b %s1, 80(, %s0)
-; CHECK-NEXT: st2b %s1, 78(, %s0)
-; CHECK-NEXT: st2b %s1, 76(, %s0)
-; CHECK-NEXT: st2b %s1, 74(, %s0)
-; CHECK-NEXT: st2b %s1, 72(, %s0)
-; CHECK-NEXT: st2b %s1, 70(, %s0)
-; CHECK-NEXT: st2b %s1, 68(, %s0)
-; CHECK-NEXT: st2b %s1, 66(, %s0)
-; CHECK-NEXT: st2b %s1, 64(, %s0)
-; CHECK-NEXT: st2b %s1, 62(, %s0)
-; CHECK-NEXT: st2b %s1, 60(, %s0)
-; CHECK-NEXT: st2b %s1, 58(, %s0)
-; CHECK-NEXT: st2b %s1, 56(, %s0)
-; CHECK-NEXT: st2b %s1, 54(, %s0)
-; CHECK-NEXT: st2b %s1, 52(, %s0)
-; CHECK-NEXT: st2b %s1, 50(, %s0)
-; CHECK-NEXT: st2b %s1, 48(, %s0)
-; CHECK-NEXT: st2b %s1, 46(, %s0)
-; CHECK-NEXT: st2b %s1, 44(, %s0)
-; CHECK-NEXT: st2b %s1, 42(, %s0)
-; CHECK-NEXT: st2b %s1, 40(, %s0)
-; CHECK-NEXT: st2b %s1, 38(, %s0)
-; CHECK-NEXT: st2b %s1, 36(, %s0)
-; CHECK-NEXT: st2b %s1, 34(, %s0)
-; CHECK-NEXT: st2b %s1, 32(, %s0)
-; CHECK-NEXT: st2b %s1, 30(, %s0)
-; CHECK-NEXT: st2b %s1, 28(, %s0)
-; CHECK-NEXT: st2b %s1, 26(, %s0)
-; CHECK-NEXT: st2b %s1, 24(, %s0)
-; CHECK-NEXT: st2b %s1, 22(, %s0)
-; CHECK-NEXT: st2b %s1, 20(, %s0)
-; CHECK-NEXT: st2b %s1, 18(, %s0)
-; CHECK-NEXT: st2b %s1, 16(, %s0)
-; CHECK-NEXT: st2b %s1, 14(, %s0)
-; CHECK-NEXT: st2b %s1, 12(, %s0)
-; CHECK-NEXT: st2b %s1, 10(, %s0)
-; CHECK-NEXT: st2b %s1, 8(, %s0)
-; CHECK-NEXT: st2b %s1, 6(, %s0)
-; CHECK-NEXT: st2b %s1, 4(, %s0)
-; CHECK-NEXT: st2b %s1, 2(, %s0)
-; CHECK-NEXT: st2b %s1, (, %s0)
-; CHECK-NEXT: b.l.t (, %s10)
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: st2b %s1, 254(, %s0)
+; CHECK-NEXT: st2b %s1, 252(, %s0)
+; CHECK-NEXT: st2b %s1, 250(, %s0)
+; CHECK-NEXT: st2b %s1, 248(, %s0)
+; CHECK-NEXT: st2b %s1, 246(, %s0)
+; CHECK-NEXT: st2b %s1, 244(, %s0)
+; CHECK-NEXT: st2b %s1, 242(, %s0)
+; CHECK-NEXT: st2b %s1, 240(, %s0)
+; CHECK-NEXT: st2b %s1, 238(, %s0)
+; CHECK-NEXT: st2b %s1, 236(, %s0)
+; CHECK-NEXT: st2b %s1, 234(, %s0)
+; CHECK-NEXT: st2b %s1, 232(, %s0)
+; CHECK-NEXT: st2b %s1, 230(, %s0)
+; CHECK-NEXT: st2b %s1, 228(, %s0)
+; CHECK-NEXT: st2b %s1, 226(, %s0)
+; CHECK-NEXT: st2b %s1, 224(, %s0)
+; CHECK-NEXT: st2b %s1, 222(, %s0)
+; CHECK-NEXT: st2b %s1, 220(, %s0)
+; CHECK-NEXT: st2b %s1, 218(, %s0)
+; CHECK-NEXT: st2b %s1, 216(, %s0)
+; CHECK-NEXT: st2b %s1, 214(, %s0)
+; CHECK-NEXT: st2b %s1, 212(, %s0)
+; CHECK-NEXT: st2b %s1, 210(, %s0)
+; CHECK-NEXT: st2b %s1, 208(, %s0)
+; CHECK-NEXT: st2b %s1, 206(, %s0)
+; CHECK-NEXT: st2b %s1, 204(, %s0)
+; CHECK-NEXT: st2b %s1, 202(, %s0)
+; CHECK-NEXT: st2b %s1, 200(, %s0)
+; CHECK-NEXT: st2b %s1, 198(, %s0)
+; CHECK-NEXT: st2b %s1, 196(, %s0)
+; CHECK-NEXT: st2b %s1, 194(, %s0)
+; CHECK-NEXT: st2b %s1, 192(, %s0)
+; CHECK-NEXT: st2b %s1, 190(, %s0)
+; CHECK-NEXT: st2b %s1, 188(, %s0)
+; CHECK-NEXT: st2b %s1, 186(, %s0)
+; CHECK-NEXT: st2b %s1, 184(, %s0)
+; CHECK-NEXT: st2b %s1, 182(, %s0)
+; CHECK-NEXT: st2b %s1, 180(, %s0)
+; CHECK-NEXT: st2b %s1, 178(, %s0)
+; CHECK-NEXT: st2b %s1, 176(, %s0)
+; CHECK-NEXT: st2b %s1, 174(, %s0)
+; CHECK-NEXT: st2b %s1, 172(, %s0)
+; CHECK-NEXT: st2b %s1, 170(, %s0)
+; CHECK-NEXT: st2b %s1, 168(, %s0)
+; CHECK-NEXT: st2b %s1, 166(, %s0)
+; CHECK-NEXT: st2b %s1, 164(, %s0)
+; CHECK-NEXT: st2b %s1, 162(, %s0)
+; CHECK-NEXT: st2b %s1, 160(, %s0)
+; CHECK-NEXT: st2b %s1, 158(, %s0)
+; CHECK-NEXT: st2b %s1, 156(, %s0)
+; CHECK-NEXT: st2b %s1, 154(, %s0)
+; CHECK-NEXT: st2b %s1, 152(, %s0)
+; CHECK-NEXT: st2b %s1, 150(, %s0)
+; CHECK-NEXT: st2b %s1, 148(, %s0)
+; CHECK-NEXT: st2b %s1, 146(, %s0)
+; CHECK-NEXT: st2b %s1, 144(, %s0)
+; CHECK-NEXT: st2b %s1, 142(, %s0)
+; CHECK-NEXT: st2b %s1, 140(, %s0)
+; CHECK-NEXT: st2b %s1, 138(, %s0)
+; CHECK-NEXT: st2b %s1, 136(, %s0)
+; CHECK-NEXT: st2b %s1, 134(, %s0)
+; CHECK-NEXT: st2b %s1, 132(, %s0)
+; CHECK-NEXT: st2b %s1, 130(, %s0)
+; CHECK-NEXT: st2b %s1, 128(, %s0)
+; CHECK-NEXT: st2b %s1, 126(, %s0)
+; CHECK-NEXT: st2b %s1, 124(, %s0)
+; CHECK-NEXT: st2b %s1, 122(, %s0)
+; CHECK-NEXT: st2b %s1, 120(, %s0)
+; CHECK-NEXT: st2b %s1, 118(, %s0)
+; CHECK-NEXT: st2b %s1, 116(, %s0)
+; CHECK-NEXT: st2b %s1, 114(, %s0)
+; CHECK-NEXT: st2b %s1, 112(, %s0)
+; CHECK-NEXT: st2b %s1, 110(, %s0)
+; CHECK-NEXT: st2b %s1, 108(, %s0)
+; CHECK-NEXT: st2b %s1, 106(, %s0)
+; CHECK-NEXT: st2b %s1, 104(, %s0)
+; CHECK-NEXT: st2b %s1, 102(, %s0)
+; CHECK-NEXT: st2b %s1, 100(, %s0)
+; CHECK-NEXT: st2b %s1, 98(, %s0)
+; CHECK-NEXT: st2b %s1, 96(, %s0)
+; CHECK-NEXT: st2b %s1, 94(, %s0)
+; CHECK-NEXT: st2b %s1, 92(, %s0)
+; CHECK-NEXT: st2b %s1, 90(, %s0)
+; CHECK-NEXT: st2b %s1, 88(, %s0)
+; CHECK-NEXT: st2b %s1, 86(, %s0)
+; CHECK-NEXT: st2b %s1, 84(, %s0)
+; CHECK-NEXT: st2b %s1, 82(, %s0)
+; CHECK-NEXT: st2b %s1, 80(, %s0)
+; CHECK-NEXT: st2b %s1, 78(, %s0)
+; CHECK-NEXT: st2b %s1, 76(, %s0)
+; CHECK-NEXT: st2b %s1, 74(, %s0)
+; CHECK-NEXT: st2b %s1, 72(, %s0)
+; CHECK-NEXT: st2b %s1, 70(, %s0)
+; CHECK-NEXT: st2b %s1, 68(, %s0)
+; CHECK-NEXT: st2b %s1, 66(, %s0)
+; CHECK-NEXT: st2b %s1, 64(, %s0)
+; CHECK-NEXT: st2b %s1, 62(, %s0)
+; CHECK-NEXT: st2b %s1, 60(, %s0)
+; CHECK-NEXT: st2b %s1, 58(, %s0)
+; CHECK-NEXT: st2b %s1, 56(, %s0)
+; CHECK-NEXT: st2b %s1, 54(, %s0)
+; CHECK-NEXT: st2b %s1, 52(, %s0)
+; CHECK-NEXT: st2b %s1, 50(, %s0)
+; CHECK-NEXT: st2b %s1, 48(, %s0)
+; CHECK-NEXT: st2b %s1, 46(, %s0)
+; CHECK-NEXT: st2b %s1, 44(, %s0)
+; CHECK-NEXT: st2b %s1, 42(, %s0)
+; CHECK-NEXT: st2b %s1, 40(, %s0)
+; CHECK-NEXT: st2b %s1, 38(, %s0)
+; CHECK-NEXT: st2b %s1, 36(, %s0)
+; CHECK-NEXT: st2b %s1, 34(, %s0)
+; CHECK-NEXT: st2b %s1, 32(, %s0)
+; CHECK-NEXT: st2b %s1, 30(, %s0)
+; CHECK-NEXT: st2b %s1, 28(, %s0)
+; CHECK-NEXT: st2b %s1, 26(, %s0)
+; CHECK-NEXT: st2b %s1, 24(, %s0)
+; CHECK-NEXT: st2b %s1, 22(, %s0)
+; CHECK-NEXT: st2b %s1, 20(, %s0)
+; CHECK-NEXT: st2b %s1, 18(, %s0)
+; CHECK-NEXT: st2b %s1, 16(, %s0)
+; CHECK-NEXT: st2b %s1, 14(, %s0)
+; CHECK-NEXT: st2b %s1, 12(, %s0)
+; CHECK-NEXT: st2b %s1, 10(, %s0)
+; CHECK-NEXT: st2b %s1, 8(, %s0)
+; CHECK-NEXT: st2b %s1, 6(, %s0)
+; CHECK-NEXT: st2b %s1, 4(, %s0)
+; CHECK-NEXT: st2b %s1, 2(, %s0)
+; CHECK-NEXT: st2b %s1, (, %s0)
+; CHECK-NEXT: b.l.t (, %s10)
%val = insertelement <128 x i16> undef, i16 %s, i32 0
%ret = shufflevector <128 x i16> %val, <128 x i16> undef, <128 x i32> zeroinitializer
ret <128 x i16> %ret
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