[llvm-branch-commits] [llvm] 4a1d230 - [VE][NFC] Modify function order and simplify comments

[Kazushi Marukawa via llvm-branch-commits]

Author: Kazushi (Jam) Marukawa
Date: 2020-11-21T16:09:37+09:00
New Revision: 4a1d230fa6f4cf27e4ce0626afe6c1434eab29b2

URL: https://github.com/llvm/llvm-project/commit/4a1d230fa6f4cf27e4ce0626afe6c1434eab29b2
DIFF: https://github.com/llvm/llvm-project/commit/4a1d230fa6f4cf27e4ce0626afe6c1434eab29b2.diff

LOG: [VE][NFC] Modify function order and simplify comments

Added: 
    

Modified: 
    llvm/lib/Target/VE/VEISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index c41d0a416eaa..eb47d01afc77 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -801,30 +801,6 @@ bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
   return true;
 }
 
-bool VETargetLowering::hasAndNot(SDValue Y) const {
-  EVT VT = Y.getValueType();
-
-  // VE doesn't have vector and not instruction.
-  if (VT.isVector())
-    return false;
-
-  // VE allows 
diff erent immediate values for X and Y where ~X & Y.
-  // Only simm7 works for X, and only mimm works for Y on VE.  However, this
-  // function is used to check whether an immediate value is OK for and-not
-  // instruction as both X and Y.  Generating additional instruction to
-  // retrieve an immediate value is no good since the purpose of this
-  // function is to convert a series of 3 instructions to another series of
-  // 3 instructions with better parallelism.  Therefore, we return false
-  // for all immediate values now.
-  // FIXME: Change hasAndNot function to have two operands to make it work
-  //        correctly with Aurora VE.
-  if (isa<ConstantSDNode>(Y))
-    return false;
-
-  // It's ok for generic registers.
-  return true;
-}
-
 VETargetLowering::VETargetLowering(const TargetMachine &TM,
                                    const VESubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
@@ -1617,7 +1593,7 @@ SDValue VETargetLowering::PerformDAGCombine(SDNode *N,
 }
 
 //===----------------------------------------------------------------------===//
-//                         VE Inline Assembly Support
+// VE Inline Assembly Support
 //===----------------------------------------------------------------------===//
 
 VETargetLowering::ConstraintType
@@ -1666,3 +1642,27 @@ unsigned VETargetLowering::getMinimumJumpTableEntries() const {
 
   return TargetLowering::getMinimumJumpTableEntries();
 }
+
+bool VETargetLowering::hasAndNot(SDValue Y) const {
+  EVT VT = Y.getValueType();
+
+  // VE doesn't have vector and not instruction.
+  if (VT.isVector())
+    return false;
+
+  // VE allows 
diff erent immediate values for X and Y where ~X & Y.
+  // Only simm7 works for X, and only mimm works for Y on VE.  However, this
+  // function is used to check whether an immediate value is OK for and-not
+  // instruction as both X and Y.  Generating additional instruction to
+  // retrieve an immediate value is no good since the purpose of this
+  // function is to convert a series of 3 instructions to another series of
+  // 3 instructions with better parallelism.  Therefore, we return false
+  // for all immediate values now.
+  // FIXME: Change hasAndNot function to have two operands to make it work
+  //        correctly with Aurora VE.
+  if (isa<ConstantSDNode>(Y))
+    return false;
+
+  // It's ok for generic registers.
+  return true;
+}