[llvm-branch-commits] [llvm] db30641 - [NFC][AArch64] Replace some template methods/invocations...
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jul 31 08:36:09 PDT 2020
Author: Francesco Petrogalli
Date: 2020-07-31T17:27:52+02:00
New Revision: db306412bf65f4b6fa4314dd5611752448bbc80c
URL: https://github.com/llvm/llvm-project/commit/db306412bf65f4b6fa4314dd5611752448bbc80c
DIFF: https://github.com/llvm/llvm-project/commit/db306412bf65f4b6fa4314dd5611752448bbc80c.diff
LOG: [NFC][AArch64] Replace some template methods/invocations...
...with the non-template version, as the template version might
increase the size of the compiler build.
Methods affected:
1.`findAddrModeSVELoadStore`
2. `SelectPredicatedStore`
Also, remove the `const` qualifier from the `unsigned` parameters of
the methods to conform with other similar methods in the class.
(cherry picked from commit dbeb184b7f54db2d3ef20ac153b1c77f81cf0b99)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 10c477853353..dbd7db7ee8e6 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -262,14 +262,12 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
- template <unsigned Scale>
- void SelectPredicatedStore(SDNode *N, unsigned NumVecs, const unsigned Opc_rr,
- const unsigned Opc_ri);
- template <unsigned Scale>
+ void SelectPredicatedStore(SDNode *N, unsigned NumVecs, unsigned Scale,
+ unsigned Opc_rr, unsigned Opc_ri);
std::tuple<unsigned, SDValue, SDValue>
- findAddrModeSVELoadStore(SDNode *N, const unsigned Opc_rr,
- const unsigned Opc_ri, const SDValue &OldBase,
- const SDValue &OldOffset);
+ findAddrModeSVELoadStore(SDNode *N, unsigned Opc_rr, unsigned Opc_ri,
+ const SDValue &OldBase, const SDValue &OldOffset,
+ unsigned Scale);
bool tryBitfieldExtractOp(SDNode *N);
bool tryBitfieldExtractOpFromSExt(SDNode *N);
@@ -1414,12 +1412,12 @@ void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
/// Optimize \param OldBase and \param OldOffset selecting the best addressing
/// mode. Returns a tuple consisting of an Opcode, an SDValue representing the
/// new Base and an SDValue representing the new offset.
-template <unsigned Scale>
std::tuple<unsigned, SDValue, SDValue>
-AArch64DAGToDAGISel::findAddrModeSVELoadStore(SDNode *N, const unsigned Opc_rr,
- const unsigned Opc_ri,
+AArch64DAGToDAGISel::findAddrModeSVELoadStore(SDNode *N, unsigned Opc_rr,
+ unsigned Opc_ri,
const SDValue &OldBase,
- const SDValue &OldOffset) {
+ const SDValue &OldOffset,
+ unsigned Scale) {
SDValue NewBase = OldBase;
SDValue NewOffset = OldOffset;
// Detect a possible Reg+Imm addressing mode.
@@ -1429,7 +1427,7 @@ AArch64DAGToDAGISel::findAddrModeSVELoadStore(SDNode *N, const unsigned Opc_rr,
// Detect a possible reg+reg addressing mode, but only if we haven't already
// detected a Reg+Imm one.
const bool IsRegReg =
- !IsRegImm && SelectSVERegRegAddrMode<Scale>(OldBase, NewBase, NewOffset);
+ !IsRegImm && SelectSVERegRegAddrMode(OldBase, Scale, NewBase, NewOffset);
// Select the instruction.
return std::make_tuple(IsRegReg ? Opc_rr : Opc_ri, NewBase, NewOffset);
@@ -1479,10 +1477,9 @@ void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
ReplaceNode(N, St);
}
-template <unsigned Scale>
void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,
- const unsigned Opc_rr,
- const unsigned Opc_ri) {
+ unsigned Scale, unsigned Opc_rr,
+ unsigned Opc_ri) {
SDLoc dl(N);
// Form a REG_SEQUENCE to force register allocation.
@@ -1492,9 +1489,9 @@ void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,
// Optimize addressing mode.
unsigned Opc;
SDValue Offset, Base;
- std::tie(Opc, Base, Offset) = findAddrModeSVELoadStore<Scale>(
+ std::tie(Opc, Base, Offset) = findAddrModeSVELoadStore(
N, Opc_rr, Opc_ri, N->getOperand(NumVecs + 3),
- CurDAG->getTargetConstant(0, dl, MVT::i64));
+ CurDAG->getTargetConstant(0, dl, MVT::i64), Scale);
SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate
Base, // address
@@ -4085,63 +4082,51 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
}
case Intrinsic::aarch64_sve_st2: {
if (VT == MVT::nxv16i8) {
- SelectPredicatedStore</*Scale=*/0>(Node, 2, AArch64::ST2B,
- AArch64::ST2B_IMM);
+ SelectPredicatedStore(Node, 2, 0, AArch64::ST2B, AArch64::ST2B_IMM);
return;
} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
(VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
- SelectPredicatedStore</*Scale=*/1>(Node, 2, AArch64::ST2H,
- AArch64::ST2H_IMM);
+ SelectPredicatedStore(Node, 2, 1, AArch64::ST2H, AArch64::ST2H_IMM);
return;
} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
- SelectPredicatedStore</*Scale=*/2>(Node, 2, AArch64::ST2W,
- AArch64::ST2W_IMM);
+ SelectPredicatedStore(Node, 2, 2, AArch64::ST2W, AArch64::ST2W_IMM);
return;
} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
- SelectPredicatedStore</*Scale=*/3>(Node, 2, AArch64::ST2D,
- AArch64::ST2D_IMM);
+ SelectPredicatedStore(Node, 2, 3, AArch64::ST2D, AArch64::ST2D_IMM);
return;
}
break;
}
case Intrinsic::aarch64_sve_st3: {
if (VT == MVT::nxv16i8) {
- SelectPredicatedStore</*Scale=*/0>(Node, 3, AArch64::ST3B,
- AArch64::ST3B_IMM);
+ SelectPredicatedStore(Node, 3, 0, AArch64::ST3B, AArch64::ST3B_IMM);
return;
} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
(VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
- SelectPredicatedStore</*Scale=*/1>(Node, 3, AArch64::ST3H,
- AArch64::ST3H_IMM);
+ SelectPredicatedStore(Node, 3, 1, AArch64::ST3H, AArch64::ST3H_IMM);
return;
} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
- SelectPredicatedStore</*Scale=*/2>(Node, 3, AArch64::ST3W,
- AArch64::ST3W_IMM);
+ SelectPredicatedStore(Node, 3, 2, AArch64::ST3W, AArch64::ST3W_IMM);
return;
} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
- SelectPredicatedStore</*Scale=*/3>(Node, 3, AArch64::ST3D,
- AArch64::ST3D_IMM);
+ SelectPredicatedStore(Node, 3, 3, AArch64::ST3D, AArch64::ST3D_IMM);
return;
}
break;
}
case Intrinsic::aarch64_sve_st4: {
if (VT == MVT::nxv16i8) {
- SelectPredicatedStore</*Scale=*/0>(Node, 4, AArch64::ST4B,
- AArch64::ST4B_IMM);
+ SelectPredicatedStore(Node, 4, 0, AArch64::ST4B, AArch64::ST4B_IMM);
return;
} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
(VT == MVT::nxv8bf16 && Subtarget->hasBF16())) {
- SelectPredicatedStore</*Scale=*/1>(Node, 4, AArch64::ST4H,
- AArch64::ST4H_IMM);
+ SelectPredicatedStore(Node, 4, 1, AArch64::ST4H, AArch64::ST4H_IMM);
return;
} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
- SelectPredicatedStore</*Scale=*/2>(Node, 4, AArch64::ST4W,
- AArch64::ST4W_IMM);
+ SelectPredicatedStore(Node, 4, 2, AArch64::ST4W, AArch64::ST4W_IMM);
return;
} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
- SelectPredicatedStore</*Scale=*/3>(Node, 4, AArch64::ST4D,
- AArch64::ST4D_IMM);
+ SelectPredicatedStore(Node, 4, 3, AArch64::ST4D, AArch64::ST4D_IMM);
return;
}
break;
More information about the llvm-branch-commits
mailing list