[llvm-branch-commits] [llvm] 59521a0 - [InstCombine] update datalayout in test file; NFC

Hans Wennborg via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Thu Jul 16 08:08:49 PDT 2020


Author: Sanjay Patel
Date: 2020-07-16T17:06:21+02:00
New Revision: 59521a06026e3912319db118340d48430838db09

URL: https://github.com/llvm/llvm-project/commit/59521a06026e3912319db118340d48430838db09
DIFF: https://github.com/llvm/llvm-project/commit/59521a06026e3912319db118340d48430838db09.diff

LOG: [InstCombine] update datalayout in test file; NFC

We need to specify legal integer widths to trigger PR46712,
so add those here. This doesn't appear to affect any existing
tests, and it's not clear why a datalayout would not include
any legal integer widths.

While here, change some variable names that include 'tmp' to
avoid warnings from the auto-generating script for CHECK lines.

(cherry picked from commit efc30e591bb5a6e869fd8e084bd310ae516b0fae)

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/or.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll
index 8037af681465..b747c5d97810 100644
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n32:64"
 
 define i32 @test12(i32 %A) {
         ; Should be eliminated
@@ -107,17 +107,17 @@ define i32 @test20(i32 %x) {
   ret i32 %z
 }
 
-define i32 @test21(i32 %tmp.1) {
+define i32 @test21(i32 %t1) {
 ; CHECK-LABEL: @test21(
-; CHECK-NEXT:    [[TMP_1_MASK1:%.*]] = add i32 [[TMP_1:%.*]], 2
-; CHECK-NEXT:    ret i32 [[TMP_1_MASK1]]
+; CHECK-NEXT:    [[T1_MASK1:%.*]] = add i32 [[T1:%.*]], 2
+; CHECK-NEXT:    ret i32 [[T1_MASK1]]
 ;
-  %tmp.1.mask1 = add i32 %tmp.1, 2
-  %tmp.3 = and i32 %tmp.1.mask1, -2
-  %tmp.5 = and i32 %tmp.1, 1
+  %t1.mask1 = add i32 %t1, 2
+  %t3 = and i32 %t1.mask1, -2
+  %t5 = and i32 %t1, 1
   ;; add tmp.1, 2
-  %tmp.6 = or i32 %tmp.5, %tmp.3
-  ret i32 %tmp.6
+  %t6 = or i32 %t5, %t3
+  ret i32 %t6
 }
 
 define i32 @test22(i32 %B) {


        


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