[llvm-branch-commits] [llvm] 5cfd30a - [RISCV] Add Clang and LLVM Release Notes

Sam Elliott via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Wed Feb 26 10:20:07 PST 2020

Author: Sam Elliott
Date: 2020-02-26T18:19:07Z
New Revision: 5cfd30add460640264c7d88c4d837a2d4e0ae7b1

URL: https://github.com/llvm/llvm-project/commit/5cfd30add460640264c7d88c4d837a2d4e0ae7b1
DIFF: https://github.com/llvm/llvm-project/commit/5cfd30add460640264c7d88c4d837a2d4e0ae7b1.diff

LOG: [RISCV] Add Clang and LLVM Release Notes




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index b160588b22c5..c9d0461b65aa 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -122,6 +122,9 @@ Non-comprehensive list of changes in this release
 * For the WebAssembly target, the ``wasm-opt`` tool will now be run if it is
   found in the PATH, which can reduce code size.
+* For the RISC-V target, floating point registers can now be used in inline
+  assembly constraints.
 New Compiler Flags
@@ -141,6 +144,13 @@ New Compiler Flags
   please let us know if you encounter a situation where you need to specify this
   flag for correct program behavior.
+- The `-ffixed-xX` flags now work on RISC-V. These reserve the corresponding
+  general-purpose registers.
+- RISC-V has added `-mcmodel=medany` and `-mcmodel=medlow` as aliases for
+  `-mcmodel=small` and `-mcmodel=medium` respectively. Preprocessor definitions
+  for `__riscv_cmodel_medlow` and `__riscv_cmodel_medany` have been corrected.
 Deprecated Compiler Flags
@@ -182,6 +192,12 @@ Modified Compiler Flags
   which is one level below ``-debug-info-kind=limited``. This option causes
   debug info for classes to be emitted only when a constructor is emitted.
+- RISC-V now chooses a slightly 
diff erent sysroot path and defaults to using
+  compiler-rt if no GCC installation is detected.
+- RISC-V now supports multilibs in baremetal environments. This support does not
+  extend to supporting multilib aliases.
 New Pragmas in Clang
@@ -309,6 +325,11 @@ ABI Changes in Clang
   `-mabi=` when compiling for RISC-V, due to how extensible this architecture
+- RISC-V now uses `target-abi` module metadata to encode the chosen psABI. This
+  ensures that the correct lowering will be done by LLVM when LTO is enabled.
+- An issue with lowering return types in the RISC-V ILP32D psABI has been fixed.
 OpenMP Support in Clang

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 6ade99ab174f..69a055aeef63 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -252,6 +252,65 @@ Changes to the Windows Target
 * Fixed section relative relocations in .debug_frame in DWARF debug info
+Changes to the RISC-V Target
+New Features:
+* The Machine Outliner has been enabled.
+* Shrink-wrapping has been enabled.
+* The Machine Scheduler has been enabled and scheduler descriptions for the
+  Rocket micro-architecture have been added, covering both 32- and 64-bit Rocket
+  cores.
+* This release lays the groundwork for enabling LTO in a future LLVM release.
+  In particular, LLVM now uses a new `target-abi` module metadata item to
+  represent the chosen RISC-V psABI variant. Frontends should add this module
+  flag to prevent ABI lowering problems when LTO is enabled in a future LLVM
+  release.
+* Support has been added for assembling RVC HINT instructions.
+* Added code lowering for half-precision floats.
+* The `fscsr` and `frcsr` (`fssr`, `frsr`) obsolete aliases have been added to
+  the assembler for use in legacy code.
+* The stack can now be realigned even when there are variable-sized objects in
+  the same frame.
+* fastcc is now supported.
+* llvm-objdump now supports `-M no-aliases` and `-M numeric` for altering the
+  dumped assembly. These match the behaviour of GNU objdump.
+* Trap and Debugtrap now lower to RISC-V-specific trap instructions.
+* LLVM IR Inline assembly now supports using ABI register names and using
+  floating point registers in constraints.
+* Stack Pointer adjustments have been changed to better match RISC-V's immediates.
+* `ra` (`x1`) can now be used as a callee-saved register.
+* The assembler now suggests spelling corrections for unknown assembly
+  mnemonics.
+* Stack offsets of greater than 32-bits are now accepted on RV64.
+* Some variadic functions can now be tail-call optimised.
+* We now custom-lower 32-bit arithmetic operations on RV64 to reduce
+  sign-extensions.
+Bug Fixes:
+* There was an issue with register preservation after calls in interrupt
+  handlers, where some registers were marked as preserved even though they were
+  not being preserved by the call. This has been corrected, and now only
+  callee-saved registers are live over a function call in an interrupt handler
+  (just like calls in regular functions).
+* Atomic instructions now only accept GPRs (plus an offset) in memory operands.
+* Fixed some issues with evalutaion of relocations and fixups.
+* The error messages around missing RISC-V extensions in the assembler have been
+  improved.
+* The error messages around unsupported relocations have been improved.
+* Non-PIC code no longer forces Local Exec TLS.
+* There have been some small changes to the code generation for atomic
+  operations.
+* RISC-V no longer emits incorrect CFI directives in function prologs and
+  epilogs.
+* RV64 no longer clears the upper bits when returning complex types from
+  libcalls using the LP64 psABI.
 Changes to the OCaml bindings


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