[llvm-branch-commits] [llvm] bf1160c - [test] Add explicit dso_local to definitions in ELF static relocation model tests
Fangrui Song via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Dec 30 17:02:31 PST 2020
Author: Fangrui Song
Date: 2020-12-30T16:52:23-08:00
New Revision: bf1160c1d6b23bd5290584b158ea204adb41b7d0
URL: https://github.com/llvm/llvm-project/commit/bf1160c1d6b23bd5290584b158ea204adb41b7d0
DIFF: https://github.com/llvm/llvm-project/commit/bf1160c1d6b23bd5290584b158ea204adb41b7d0.diff
LOG: [test] Add explicit dso_local to definitions in ELF static relocation model tests
Added:
Modified:
llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
llvm/test/CodeGen/PowerPC/dsolocal-static.ll
llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll b/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
index bda4c6d47237..e8ac7b6bbf5e 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
@@ -56,12 +56,14 @@ define void @t2() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG1:r[0-9]+]], [r0]
+; ARM-MACHO: add r0, [[REG1]], #4
+; ARM-MACHO-NEXT: add r1, [[REG1]], #16
; ARM-ELF: movw [[REG1:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG1]], :upper16:temp
+; ARM-ELF: add r0, [[REG1]], #4
+; ARM-ELF-NEXT: add r1, [[REG1]], #16
-; ARM: add r0, [[REG1]], #4
-; ARM: add r1, [[REG1]], #16
; ARM: movw r2, #17
; ARM: bl {{_?}}memcpy
; ARM-LONG-LABEL: t2:
@@ -99,13 +101,14 @@ define void @t3() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
+; ARM-MACHO: add r0, [[REG0]], #4
+; ARM-MACHO-NEXT: add r1, [[REG0]], #16
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp
+; ARM-ELF: add r0, [[REG0]], #4
+; ARM-ELF-NEXT: add r1, r1, #16
-
-; ARM: add r0, [[REG0]], #4
-; ARM: add r1, [[REG0]], #16
; ARM: movw r2, #10
; ARM: bl {{_?}}memmove
; ARM-LONG-LABEL: t3:
@@ -140,17 +143,17 @@ define void @t4() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
-; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
+; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
+; ARM-MACHO-NEXT: ldr [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
+; ARM-MACHO-NEXT: str [[REG1]], {{\[}}[[REG0]], #4]
+; ARM-MACHO-NEXT: ldr [[REG2:r[0-9]+]], {{\[}}[[REG0]], #20]
+; ARM-MACHO-NEXT: str [[REG2]], {{\[}}[[REG0]], #8]
+; ARM-MACHO-NEXT: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #24]
+; ARM-MACHO-NEXT: strh [[REG3]], {{\[}}[[REG0]], #12]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp
-; ARM: ldr [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
-; ARM: str [[REG1]], {{\[}}[[REG0]], #4]
-; ARM: ldr [[REG2:r[0-9]+]], {{\[}}[[REG0]], #20]
-; ARM: str [[REG2]], {{\[}}[[REG0]], #8]
-; ARM: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #24]
-; ARM: strh [[REG3]], {{\[}}[[REG0]], #12]
; ARM: bx lr
; THUMB-LABEL: t4:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
@@ -175,20 +178,20 @@ define void @t5() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
+; ARM-MACHO: ldrh [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
+; ARM-MACHO-NEXT: strh [[REG1]], {{\[}}[[REG0]], #4]
+; ARM-MACHO-NEXT: ldrh [[REG2:r[0-9]+]], {{\[}}[[REG0]], #18]
+; ARM-MACHO-NEXT: strh [[REG2]], {{\[}}[[REG0]], #6]
+; ARM-MACHO-NEXT: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #20]
+; ARM-MACHO-NEXT: strh [[REG3]], {{\[}}[[REG0]], #8]
+; ARM-MACHO-NEXT: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG0]], #22]
+; ARM-MACHO-NEXT: strh [[REG4]], {{\[}}[[REG0]], #10]
+; ARM-MACHO-NEXT: ldrh [[REG5:r[0-9]+]], {{\[}}[[REG0]], #24]
+; ARM-MACHO-NEXT: strh [[REG5]], {{\[}}[[REG0]], #12]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp
-; ARM: ldrh [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
-; ARM: strh [[REG1]], {{\[}}[[REG0]], #4]
-; ARM: ldrh [[REG2:r[0-9]+]], {{\[}}[[REG0]], #18]
-; ARM: strh [[REG2]], {{\[}}[[REG0]], #6]
-; ARM: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #20]
-; ARM: strh [[REG3]], {{\[}}[[REG0]], #8]
-; ARM: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG0]], #22]
-; ARM: strh [[REG4]], {{\[}}[[REG0]], #10]
-; ARM: ldrh [[REG5:r[0-9]+]], {{\[}}[[REG0]], #24]
-; ARM: strh [[REG5]], {{\[}}[[REG0]], #12]
; ARM: bx lr
; THUMB-LABEL: t5:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
@@ -215,30 +218,30 @@ define void @t6() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
+; ARM-MACHO: ldrb [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
+; ARM-MACHO-NEXT: strb [[REG1]], {{\[}}[[REG0]], #4]
+; ARM-MACHO-NEXT: ldrb [[REG2:r[0-9]+]], {{\[}}[[REG0]], #17]
+; ARM-MACHO-NEXT: strb [[REG2]], {{\[}}[[REG0]], #5]
+; ARM-MACHO-NEXT: ldrb [[REG3:r[0-9]+]], {{\[}}[[REG0]], #18]
+; ARM-MACHO-NEXT: strb [[REG3]], {{\[}}[[REG0]], #6]
+; ARM-MACHO-NEXT: ldrb [[REG4:r[0-9]+]], {{\[}}[[REG0]], #19]
+; ARM-MACHO-NEXT: strb [[REG4]], {{\[}}[[REG0]], #7]
+; ARM-MACHO-NEXT: ldrb [[REG5:r[0-9]+]], {{\[}}[[REG0]], #20]
+; ARM-MACHO-NEXT: strb [[REG5]], {{\[}}[[REG0]], #8]
+; ARM-MACHO-NEXT: ldrb [[REG6:r[0-9]+]], {{\[}}[[REG0]], #21]
+; ARM-MACHO-NEXT: strb [[REG6]], {{\[}}[[REG0]], #9]
+; ARM-MACHO-NEXT: ldrb [[REG7:r[0-9]+]], {{\[}}[[REG0]], #22]
+; ARM-MACHO-NEXT: strb [[REG7]], {{\[}}[[REG0]], #10]
+; ARM-MACHO-NEXT: ldrb [[REG8:r[0-9]+]], {{\[}}[[REG0]], #23]
+; ARM-MACHO-NEXT: strb [[REG8]], {{\[}}[[REG0]], #11]
+; ARM-MACHO-NEXT: ldrb [[REG9:r[0-9]+]], {{\[}}[[REG0]], #24]
+; ARM-MACHO-NEXT: strb [[REG9]], {{\[}}[[REG0]], #12]
+; ARM-MACHO-NEXT: ldrb [[REG10:r[0-9]+]], {{\[}}[[REG0]], #25]
+; ARM-MACHO-NEXT: strb [[REG10]], {{\[}}[[REG0]], #13]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp
-; ARM: ldrb [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
-; ARM: strb [[REG1]], {{\[}}[[REG0]], #4]
-; ARM: ldrb [[REG2:r[0-9]+]], {{\[}}[[REG0]], #17]
-; ARM: strb [[REG2]], {{\[}}[[REG0]], #5]
-; ARM: ldrb [[REG3:r[0-9]+]], {{\[}}[[REG0]], #18]
-; ARM: strb [[REG3]], {{\[}}[[REG0]], #6]
-; ARM: ldrb [[REG4:r[0-9]+]], {{\[}}[[REG0]], #19]
-; ARM: strb [[REG4]], {{\[}}[[REG0]], #7]
-; ARM: ldrb [[REG5:r[0-9]+]], {{\[}}[[REG0]], #20]
-; ARM: strb [[REG5]], {{\[}}[[REG0]], #8]
-; ARM: ldrb [[REG6:r[0-9]+]], {{\[}}[[REG0]], #21]
-; ARM: strb [[REG6]], {{\[}}[[REG0]], #9]
-; ARM: ldrb [[REG7:r[0-9]+]], {{\[}}[[REG0]], #22]
-; ARM: strb [[REG7]], {{\[}}[[REG0]], #10]
-; ARM: ldrb [[REG8:r[0-9]+]], {{\[}}[[REG0]], #23]
-; ARM: strb [[REG8]], {{\[}}[[REG0]], #11]
-; ARM: ldrb [[REG9:r[0-9]+]], {{\[}}[[REG0]], #24]
-; ARM: strb [[REG9]], {{\[}}[[REG0]], #12]
-; ARM: ldrb [[REG10:r[0-9]+]], {{\[}}[[REG0]], #25]
-; ARM: strb [[REG10]], {{\[}}[[REG0]], #13]
; ARM: bx lr
; THUMB-LABEL: t6:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
diff --git a/llvm/test/CodeGen/PowerPC/dsolocal-static.ll b/llvm/test/CodeGen/PowerPC/dsolocal-static.ll
index 9a1b28358f73..a4ef632f6877 100644
--- a/llvm/test/CodeGen/PowerPC/dsolocal-static.ll
+++ b/llvm/test/CodeGen/PowerPC/dsolocal-static.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=ppc64le -relocation-model=static < %s | FileCheck %s
- at default = dso_local global i32 55
+ at default = global i32 55
define dso_local i32* @get_default_global() {
; CHECK-LABEL: get_default_global:
; CHECK: addis 3, 2, default at toc@ha
diff --git a/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll b/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
index c2f0ad62fd63..19a5b7fbd938 100644
--- a/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
+++ b/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
@@ -490,7 +490,7 @@ define dso_local x86_regcallcc double @test_CallargRetDouble(double %a) {
}
; Test regcall when receiving/returning long double
-define x86_regcallcc x86_fp80 @test_argRetf80(x86_fp80 %a0) nounwind {
+define dso_local x86_regcallcc x86_fp80 @test_argRetf80(x86_fp80 %a0) nounwind {
; X32-LABEL: test_argRetf80:
; X32: # %bb.0:
; X32-NEXT: fadd %st, %st(0)
@@ -620,7 +620,7 @@ define dso_local x86_regcallcc double @test_CallargParamf80(x86_fp80 %a) {
}
; Test regcall when receiving/returning pointer
-define x86_regcallcc [4 x i32]* @test_argRetPointer([4 x i32]* %a) {
+define dso_local x86_regcallcc [4 x i32]* @test_argRetPointer([4 x i32]* %a) {
; X32-LABEL: test_argRetPointer:
; X32: # %bb.0:
; X32-NEXT: incl %eax
@@ -642,7 +642,7 @@ define x86_regcallcc [4 x i32]* @test_argRetPointer([4 x i32]* %a) {
}
; Test regcall when passing/retrieving pointer
-define x86_regcallcc [4 x i32]* @test_CallargRetPointer([4 x i32]* %a) {
+define dso_local x86_regcallcc [4 x i32]* @test_CallargRetPointer([4 x i32]* %a) {
; X32-LABEL: test_CallargRetPointer:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll
index 3db3ef794b49..3790f419ddaa 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll
@@ -1,5 +1,5 @@
; RUN: llc -enable-machine-outliner -mtriple=aarch64-unknown-linux < %s | FileCheck %s
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
%1 = alloca i32, align 4
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
index 428be9ee4311..39a189d1c5f6 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
; RUN: llc -enable-machine-outliner -mtriple=aarch64-unknown-linux < %s | FileCheck %s
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
%1 = alloca i32, align 4
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
index bf4e4564086f..77568d028225 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-machine-outliner -mtriple=aarch64-unknown-linux < %s | FileCheck %s
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
; CHECK-LABEL: check_boundaries:
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll
index ed5d949bb092..88af70a5c8f1 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll
@@ -2,13 +2,13 @@
declare void @foo()
-define i64 @check_lines_1() {
+define dso_local i64 @check_lines_1() {
ret i64 1
}
; UTC_ARGS: --disable
-define i64 @no_check_lines() {
+define dso_local i64 @no_check_lines() {
; A check line that would not be auto-generated (should not be removed!).
; CHECK: manual check line
ret i64 2
@@ -16,7 +16,7 @@ define i64 @no_check_lines() {
; UTC_ARGS: --enable --no_x86_scrub_rip
-define i64 @check_lines_2() {
+define dso_local i64 @check_lines_2() {
%result = call i64 @no_check_lines()
ret i64 %result
}
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll.expected
index f1955c4af252..2d90b10e558f 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/on_the_fly_arg_change.ll.expected
@@ -3,7 +3,7 @@
declare void @foo()
-define i64 @check_lines_1() {
+define dso_local i64 @check_lines_1() {
; CHECK-LABEL: check_lines_1:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $1, %eax
@@ -14,7 +14,7 @@ define i64 @check_lines_1() {
; UTC_ARGS: --disable
-define i64 @no_check_lines() {
+define dso_local i64 @no_check_lines() {
; A check line that would not be auto-generated (should not be removed!).
; CHECK: manual check line
ret i64 2
@@ -22,7 +22,7 @@ define i64 @no_check_lines() {
; UTC_ARGS: --enable --no_x86_scrub_rip
-define i64 @check_lines_2() {
+define dso_local i64 @check_lines_2() {
; CHECK-LABEL: check_lines_2:
; CHECK: # %bb.0:
; CHECK-NEXT: calll no_check_lines
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll
index 38b0ec04887d..ecc4a03d6681 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll
@@ -1,7 +1,7 @@
; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s
;
; NOTE: Machine outliner doesn't run.
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
%1 = alloca i32, align 4
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected
index 3d6877316312..c22995e46cbd 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s
; NOTE: Machine outliner doesn't run.
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
%1 = alloca i32, align 4
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected
index 9e72b2084c52..292d558f2b9f 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected
@@ -2,7 +2,7 @@
; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s
;
; NOTE: Machine outliner doesn't run.
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
; CHECK-LABEL: check_boundaries:
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll
index fe94f5ee3a0c..82c9ed018cbe 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll
@@ -1,5 +1,5 @@
; RUN: llc -enable-machine-outliner -mtriple=x86_64-unknown-linux < %s | FileCheck %s
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
%1 = alloca i32, align 4
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected
index eb88ffcb425d..0c7ab2b13aec 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
; RUN: llc -enable-machine-outliner -mtriple=x86_64-unknown-linux < %s | FileCheck %s
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
%1 = alloca i32, align 4
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected
index bd710b4b2081..b4424dab201e 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-machine-outliner -mtriple=x86_64-unknown-linux < %s | FileCheck %s
- at x = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 {
; CHECK-LABEL: check_boundaries:
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