[llvm-branch-commits] [mlir] 58ce477 - Fix DRR pattern when attributes and operands are interleaved and a dag subtree appears in the rewrite

Mehdi Amini via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Tue Dec 29 16:27:09 PST 2020


Author: Mehdi Amini
Date: 2020-12-30T00:19:38Z
New Revision: 58ce477676c7bd9c6cee0c6d05f2708b4e178ff3

URL: https://github.com/llvm/llvm-project/commit/58ce477676c7bd9c6cee0c6d05f2708b4e178ff3
DIFF: https://github.com/llvm/llvm-project/commit/58ce477676c7bd9c6cee0c6d05f2708b4e178ff3.diff

LOG: Fix DRR pattern when attributes and operands are interleaved and a dag subtree appears in the rewrite

This fixes an incorrect fatal error in TableGen. This code probably comes
from before attributes were allowed to interleave with operands in ODS.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D93915

Added: 
    

Modified: 
    mlir/test/mlir-tblgen/rewriter-indexing.td
    mlir/tools/mlir-tblgen/RewriterGen.cpp

Removed: 
    


################################################################################
diff  --git a/mlir/test/mlir-tblgen/rewriter-indexing.td b/mlir/test/mlir-tblgen/rewriter-indexing.td
index ed493d09008b..c21b04f6d0f6 100644
--- a/mlir/test/mlir-tblgen/rewriter-indexing.td
+++ b/mlir/test/mlir-tblgen/rewriter-indexing.td
@@ -47,3 +47,11 @@ def test1 : Pat<(BOp $attr, (AOp $input)),
 // CHECK: castedOp0.getODSOperands(1).begin()).getDefiningOp()
 def test2 : Pat<(COp $attr1, $op1, $attr2, (AOp $op2)),
                 (BOp $attr1, $op2)>;
+
+
+// Check rewriting with a DAG subtree in the result and remapping a location.
+// CHECK: struct test3 : public ::mlir::RewritePattern {
+// CHECK: rewriter.create<test::BOp>((*a.getODSResults(0).begin()).getLoc()
+def test3 : Pat<(BOp $attr, (AOp:$a $input)),
+                (BOp $attr, (AOp $input), (location $a))>;
+

diff  --git a/mlir/tools/mlir-tblgen/RewriterGen.cpp b/mlir/tools/mlir-tblgen/RewriterGen.cpp
index da189c65ec2a..96488d9cedc0 100644
--- a/mlir/tools/mlir-tblgen/RewriterGen.cpp
+++ b/mlir/tools/mlir-tblgen/RewriterGen.cpp
@@ -998,7 +998,7 @@ std::string PatternEmitter::handleOpCreation(DagNode tree, int resultIndex,
   // First go through all the child nodes who are nested DAG constructs to
   // create ops for them and remember the symbol names for them, so that we can
   // use the results in the current node. This happens in a recursive manner.
-  for (int i = 0, e = resultOp.getNumOperands(); i != e; ++i) {
+  for (int i = 0, e = tree.getNumArgs() - hasLocationDirective; i != e; ++i) {
     if (auto child = tree.getArgAsNestedDag(i))
       childNodeNames[i] = handleResultPattern(child, i, depth + 1);
   }


        


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