[llvm-branch-commits] [llvm] f7f09e2 - [RISCV] Fill out basic integer RVV ISel patterns
Fraser Cormack via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Dec 29 11:42:18 PST 2020
Author: Fraser Cormack
Date: 2020-12-29T19:32:18Z
New Revision: f7f09e2b1c897f0b42be72939d0c97dcfd1577f7
URL: https://github.com/llvm/llvm-project/commit/f7f09e2b1c897f0b42be72939d0c97dcfd1577f7
DIFF: https://github.com/llvm/llvm-project/commit/f7f09e2b1c897f0b42be72939d0c97dcfd1577f7.diff
LOG: [RISCV] Fill out basic integer RVV ISel patterns
This complements the existing RVV ISel patterns for arithmetic, bitwise
and shifts with the remaining operations in those categories: sub, and,
xor, sra.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D93852
Added:
llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index b8c78451b287..61974c0a2ea9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -96,6 +96,19 @@ class VPatBinarySDNode_XI<SDNode vop,
xop_kind:$rs2,
VLMax, sew)>;
+multiclass VPatBinarySDNode_VV_VX<SDNode vop, string instruction_name>
+{
+ foreach vti = AllIntegerVectors in {
+ def : VPatBinarySDNode_VV<vop, instruction_name,
+ vti.Vector, vti.Vector, vti.Mask, vti.SEW,
+ vti.LMul, vti.RegClass, vti.RegClass>;
+ def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
+ vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
+ vti.LMul, vti.RegClass, vti.RegClass,
+ SplatPat, GPR>;
+ }
+}
+
multiclass VPatBinarySDNode_VV_VX_VI<SDNode vop, string instruction_name,
Operand ImmType = simm5>
{
@@ -127,13 +140,29 @@ defm "" : VPatUSLoadStoreSDNodes<AddrFI>;
// 12.1. Vector Single-Width Integer Add and Subtract
defm "" : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
+defm "" : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
+// Handle VRSUB specially since it's the only integer binary op with reversed
+// pattern operands
+foreach vti = AllIntegerVectors in {
+ def : Pat<(sub (vti.Vector (SplatPat XLenVT:$rs2)),
+ (vti.Vector vti.RegClass:$rs1)),
+ (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
+ vti.RegClass:$rs1, GPR:$rs2, VLMax, vti.SEW)>;
+ def : Pat<(sub (vti.Vector (SplatPat_simm5 XLenVT:$rs2)),
+ (vti.Vector vti.RegClass:$rs1)),
+ (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX)
+ vti.RegClass:$rs1, simm5:$rs2, VLMax, vti.SEW)>;
+}
// 12.5. Vector Bitwise Logical Instructions
+defm "" : VPatBinarySDNode_VV_VX_VI<and, "PseudoVAND">;
defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
+defm "" : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
// 12.6. Vector Single-Width Bit Shift Instructions
defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
+defm "" : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
} // Predicates = [HasStdExtV]
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
new file mode 100644
index 000000000000..a5124ad2cc8e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
@@ -0,0 +1,1333 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vand_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 1 x i8> %va, %vb
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vand_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vand_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vand_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv1i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vand_vi_nxv1i8_2(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv1i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 2 x i8> %va, %vb
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv2i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vi_nxv2i8_2(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv2i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 4 x i8> %va, %vb
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv4i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vi_nxv4i8_2(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv4i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 8 x i8> %va, %vb
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv8i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv8i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = and <vscale x 16 x i8> %va, %vb
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv16i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vi_nxv16i8_2(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv16i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = and <vscale x 32 x i8> %va, %vb
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv32i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vi_nxv32i8_2(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv32i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = and <vscale x 64 x i8> %va, %vb
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = and <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = and <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv64i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = and <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vi_nxv64i8_2(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv64i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = and <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vand_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 1 x i16> %va, %vb
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vand_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vand_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vand_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv1i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vand_vi_nxv1i16_2(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv1i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 2 x i16> %va, %vb
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv2i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vi_nxv2i16_2(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv2i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 4 x i16> %va, %vb
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv4i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vi_nxv4i16_2(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv4i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = and <vscale x 8 x i16> %va, %vb
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv8i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv8i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = and <vscale x 16 x i16> %va, %vb
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv16i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vi_nxv16i16_2(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv16i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = and <vscale x 32 x i16> %va, %vb
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv32i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vi_nxv32i16_2(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv32i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vand_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 1 x i32> %va, %vb
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vand_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vand_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vand_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vand_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vand_vi_nxv1i32_2(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv1i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 2 x i32> %va, %vb
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vand_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv2i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vi_nxv2i32_2(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv2i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = and <vscale x 4 x i32> %va, %vb
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vand_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vi_nxv4i32_2(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv4i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = and <vscale x 8 x i32> %va, %vb
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vand_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv8i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = and <vscale x 16 x i32> %va, %vb
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vand_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv16i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vi_nxv16i32_2(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv16i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vand_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vand_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vand_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT: vmv.v.x v25, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v25, v25, a1
+; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vsrl.vx v26, v26, a1
+; CHECK-NEXT: vor.vv v25, v26, v25
+; CHECK-NEXT: vand.vv v16, v16, v25
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vand_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 -10, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vand_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vand_vi_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vand_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = and <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vand_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT: vmv.v.x v26, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vmv.v.x v28, a0
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vsrl.vx v28, v28, a1
+; CHECK-NEXT: vor.vv v26, v28, v26
+; CHECK-NEXT: vand.vv v16, v16, v26
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 -10, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vi_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vand_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = and <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vand_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT: vmv.v.x v28, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vor.vv v28, v8, v28
+; CHECK-NEXT: vand.vv v16, v16, v28
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 -10, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vi_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vand_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = and <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vand_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vsll.vx v24, v24, a1
+; CHECK-NEXT: vsrl.vx v24, v24, a1
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 -10, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll
new file mode 100644
index 000000000000..b7032cbdc56a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll
@@ -0,0 +1,1305 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vand_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 1 x i8> %va, %vb
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vand_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vand_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vand_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv1i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vand_vi_nxv1i8_2(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv1i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 2 x i8> %va, %vb
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv2i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vand_vi_nxv2i8_2(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv2i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 4 x i8> %va, %vb
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv4i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vand_vi_nxv4i8_2(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv4i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 8 x i8> %va, %vb
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv8i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vand_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv8i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = and <vscale x 16 x i8> %va, %vb
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv16i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vand_vi_nxv16i8_2(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv16i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = and <vscale x 32 x i8> %va, %vb
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv32i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vand_vi_nxv32i8_2(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv32i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
+; CHECK-LABEL: vand_vv_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = and <vscale x 64 x i8> %va, %vb
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vand_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = and <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 -10, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = and <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv64i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = and <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vand_vi_nxv64i8_2(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vand_vi_nxv64i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = and <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vand_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 1 x i16> %va, %vb
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vand_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vand_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vand_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv1i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vand_vi_nxv1i16_2(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv1i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 2 x i16> %va, %vb
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv2i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vand_vi_nxv2i16_2(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv2i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 4 x i16> %va, %vb
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv4i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vand_vi_nxv4i16_2(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv4i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = and <vscale x 8 x i16> %va, %vb
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv8i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vand_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv8i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = and <vscale x 16 x i16> %va, %vb
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv16i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vand_vi_nxv16i16_2(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv16i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
+; CHECK-LABEL: vand_vv_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = and <vscale x 32 x i16> %va, %vb
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vand_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 -10, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv32i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vand_vi_nxv32i16_2(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vand_vi_nxv32i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = and <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vand_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 1 x i32> %va, %vb
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vand_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vand_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vand_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vand_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vand_vi_nxv1i32_2(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv1i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 2 x i32> %va, %vb
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vand_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv2i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vand_vi_nxv2i32_2(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv2i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = and <vscale x 4 x i32> %va, %vb
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vand_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vand_vi_nxv4i32_2(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv4i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = and <vscale x 8 x i32> %va, %vb
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vand_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv8i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
+; CHECK-LABEL: vand_vv_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = and <vscale x 16 x i32> %va, %vb
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vand_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 -10, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv16i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vand_vi_nxv16i32_2(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vand_vi_nxv16i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = and <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vand_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vand_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = and <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vand_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vand_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 -10, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vand_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vand_vi_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = and <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vand_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = and <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vand_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 -10, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vand_vi_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = and <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vand_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = and <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vand_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 -10, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vand_vi_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = and <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vand_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vand.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = and <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vand_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, -10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 -10, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vand.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vand_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vand_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vand.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = and <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
new file mode 100644
index 000000000000..5b66ca7ece99
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
@@ -0,0 +1,559 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vrsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i8> %splat, %va
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vrsub_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i8> %splat, %va
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vrsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i8> %splat, %va
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vrsub_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i8> %splat, %va
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vrsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i8> %splat, %va
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vrsub_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i8> %splat, %va
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vrsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i8> %splat, %va
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vrsub_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i8> %splat, %va
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vrsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i8> %splat, %va
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vrsub_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i8> %splat, %va
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vrsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i8> %splat, %va
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vrsub_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i8> %splat, %va
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vrsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = sub <vscale x 64 x i8> %splat, %va
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vrsub_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = sub <vscale x 64 x i8> %splat, %va
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vrsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i16> %splat, %va
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vrsub_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i16> %splat, %va
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vrsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i16> %splat, %va
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vrsub_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i16> %splat, %va
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vrsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i16> %splat, %va
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vrsub_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i16> %splat, %va
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vrsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i16> %splat, %va
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vrsub_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i16> %splat, %va
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vrsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i16> %splat, %va
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vrsub_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i16> %splat, %va
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vrsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i16> %splat, %va
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vrsub_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i16> %splat, %va
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vrsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vrsub_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i32> %splat, %va
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vrsub_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i32> %splat, %va
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vrsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vrsub_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i32> %splat, %va
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vrsub_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i32> %splat, %va
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vrsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vrsub_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i32> %splat, %va
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vrsub_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i32> %splat, %va
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vrsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vrsub_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %splat, %va
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vrsub_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %splat, %va
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vrsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vrsub_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i32> %splat, %va
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vrsub_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i32> %splat, %va
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vrsub_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT: vmv.v.x v25, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v25, v25, a1
+; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vsrl.vx v26, v26, a1
+; CHECK-NEXT: vor.vv v25, v26, v25
+; CHECK-NEXT: vsub.vv v16, v25, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i64> %splat, %va
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vrsub_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vrsub_vi_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 -4, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i64> %splat, %va
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vrsub_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT: vmv.v.x v26, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vmv.v.x v28, a0
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vsrl.vx v28, v28, a1
+; CHECK-NEXT: vor.vv v26, v28, v26
+; CHECK-NEXT: vsub.vv v16, v26, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i64> %splat, %va
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vrsub_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vrsub_vi_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 -4, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i64> %splat, %va
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vrsub_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT: vmv.v.x v28, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vor.vv v28, v8, v28
+; CHECK-NEXT: vsub.vv v16, v28, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i64> %splat, %va
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vrsub_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vrsub_vi_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 -4, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i64> %splat, %va
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vrsub_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vsll.vx v24, v24, a1
+; CHECK-NEXT: vsrl.vx v24, v24, a1
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsub.vv v16, v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i64> %splat, %va
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vrsub_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vrsub_vi_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 -4, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i64> %splat, %va
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll
new file mode 100644
index 000000000000..acde938f3e93
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll
@@ -0,0 +1,531 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vrsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i8> %splat, %va
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vrsub_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i8> %splat, %va
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vrsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i8> %splat, %va
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vrsub_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i8> %splat, %va
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vrsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i8> %splat, %va
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vrsub_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i8> %splat, %va
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vrsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i8> %splat, %va
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vrsub_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i8> %splat, %va
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vrsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i8> %splat, %va
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vrsub_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i8> %splat, %va
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vrsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i8> %splat, %va
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vrsub_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i8> %splat, %va
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vrsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = sub <vscale x 64 x i8> %splat, %va
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vrsub_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vrsub_vi_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 -4, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = sub <vscale x 64 x i8> %splat, %va
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vrsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i16> %splat, %va
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vrsub_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i16> %splat, %va
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vrsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i16> %splat, %va
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vrsub_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i16> %splat, %va
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vrsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i16> %splat, %va
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vrsub_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i16> %splat, %va
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vrsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i16> %splat, %va
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vrsub_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i16> %splat, %va
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vrsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i16> %splat, %va
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vrsub_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i16> %splat, %va
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vrsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i16> %splat, %va
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vrsub_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vrsub_vi_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 -4, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i16> %splat, %va
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vrsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i32> %splat, %va
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vrsub_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i32> %splat, %va
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vrsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i32> %splat, %va
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vrsub_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i32> %splat, %va
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vrsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i32> %splat, %va
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vrsub_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i32> %splat, %va
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vrsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %splat, %va
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vrsub_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %splat, %va
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vrsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vrsub_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i32> %splat, %va
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vrsub_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vrsub_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 -4, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i32> %splat, %va
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vrsub_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i64> %splat, %va
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vrsub_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vrsub_vi_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 -4, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i64> %splat, %va
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vrsub_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i64> %splat, %va
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vrsub_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vrsub_vi_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 -4, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i64> %splat, %va
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vrsub_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i64> %splat, %va
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vrsub_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vrsub_vi_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 -4, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i64> %splat, %va
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vrsub_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vrsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i64> %splat, %va
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vrsub_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vrsub_vi_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vrsub.vi v16, v16, -4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 -4, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i64> %splat, %va
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
new file mode 100644
index 000000000000..ed5ca9025f84
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
@@ -0,0 +1,1069 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vsra_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 1 x i8> %va, %vb
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsra_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsra_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsra_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsra_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 2 x i8> %va, %vb
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsra_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsra_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsra_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsra_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 4 x i8> %va, %vb
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsra_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsra_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsra_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsra_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 8 x i8> %va, %vb
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsra_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsra_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsra_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsra_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 16 x i8> %va, %vb
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsra_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsra_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsra_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsra_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 32 x i8> %va, %vb
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsra_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsra_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsra_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv32i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsra_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 64 x i8> %va, %vb
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsra_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = ashr <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsra_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = ashr <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsra_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv64i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = ashr <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 1 x i16> %va, %vb
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsra_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsra_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsra_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsra_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 2 x i16> %va, %vb
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsra_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsra_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsra_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsra_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 4 x i16> %va, %vb
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsra_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsra_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsra_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsra_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 8 x i16> %va, %vb
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsra_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsra_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsra_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsra_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 16 x i16> %va, %vb
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsra_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsra_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsra_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsra_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 32 x i16> %va, %vb
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsra_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsra_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsra_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv32i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vsra_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 1 x i32> %va, %vb
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsra_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsra_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsra_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsra_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsra_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 2 x i32> %va, %vb
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsra_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsra_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsra_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsra_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsra_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 4 x i32> %va, %vb
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsra_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsra_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsra_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsra_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 8 x i32> %va, %vb
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsra_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsra_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 16 x i32> %va, %vb
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsra_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsra_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsra_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsra_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vsra_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vsra_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsra_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsra_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT: vmv.v.x v25, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v25, v25, a1
+; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vsrl.vx v26, v26, a1
+; CHECK-NEXT: vor.vv v25, v26, v25
+; CHECK-NEXT: vsra.vv v16, v16, v25
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsra_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 31, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsra_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsra_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vsra_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsra_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsra_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT: vmv.v.x v26, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vmv.v.x v28, a0
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vsrl.vx v28, v28, a1
+; CHECK-NEXT: vor.vv v26, v28, v26
+; CHECK-NEXT: vsra.vv v16, v16, v26
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsra_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 31, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsra_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsra_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vsra_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsra_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsra_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT: vmv.v.x v28, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vor.vv v28, v8, v28
+; CHECK-NEXT: vsra.vv v16, v16, v28
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsra_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 31, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsra_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsra_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vsra_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsra_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsra_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vsll.vx v24, v24, a1
+; CHECK-NEXT: vsrl.vx v24, v24, a1
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsra_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 31, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsra_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
new file mode 100644
index 000000000000..550dcb579485
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
@@ -0,0 +1,1041 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vsra_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 1 x i8> %va, %vb
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsra_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsra_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsra_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsra_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 2 x i8> %va, %vb
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsra_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsra_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsra_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsra_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 4 x i8> %va, %vb
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsra_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsra_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsra_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsra_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 8 x i8> %va, %vb
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsra_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsra_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsra_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsra_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 16 x i8> %va, %vb
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsra_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsra_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsra_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsra_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 32 x i8> %va, %vb
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsra_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsra_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsra_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv32i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsra_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
+; CHECK-LABEL: vsra_vv_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 64 x i8> %va, %vb
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsra_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = ashr <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsra_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = ashr <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsra_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsra_vi_nxv64i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = ashr <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 1 x i16> %va, %vb
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsra_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsra_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsra_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsra_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 2 x i16> %va, %vb
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsra_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsra_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsra_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsra_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 4 x i16> %va, %vb
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsra_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsra_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsra_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsra_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 8 x i16> %va, %vb
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsra_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsra_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsra_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsra_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 16 x i16> %va, %vb
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsra_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsra_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsra_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsra_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
+; CHECK-LABEL: vsra_vv_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 32 x i16> %va, %vb
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsra_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsra_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsra_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsra_vi_nxv32i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = ashr <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vsra_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 1 x i32> %va, %vb
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsra_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsra_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsra_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsra_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 2 x i32> %va, %vb
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsra_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsra_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsra_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsra_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 4 x i32> %va, %vb
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsra_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsra_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsra_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 8 x i32> %va, %vb
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsra_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
+; CHECK-LABEL: vsra_vv_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 16 x i32> %va, %vb
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsra_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsra_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsra_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 31, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsra_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsra_vi_nxv16i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = ashr <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vsra_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vsra_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsra_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsra_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsra_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 31, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsra_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = ashr <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsra_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vsra_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsra_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsra_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsra_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 31, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsra_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = ashr <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsra_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vsra_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsra.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsra_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsra_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsra_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 31, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsra_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = ashr <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsra_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vsra_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vsra.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = ashr <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsra_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsra_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsra_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vsra.vi v16, v16, 31
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 31, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsra_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsra_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vsra.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
new file mode 100644
index 000000000000..8000ed2b2723
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
@@ -0,0 +1,805 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vsub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 1 x i8> %va, %vb
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsub_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 2 x i8> %va, %vb
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsub_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 4 x i8> %va, %vb
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsub_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 8 x i8> %va, %vb
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsub_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 16 x i8> %va, %vb
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsub_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 32 x i8> %va, %vb
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsub_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 64 x i8> %va, %vb
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = sub <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsub_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = sub <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vsub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 1 x i16> %va, %vb
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsub_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 2 x i16> %va, %vb
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsub_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 4 x i16> %va, %vb
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsub_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 8 x i16> %va, %vb
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsub_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 16 x i16> %va, %vb
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsub_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 32 x i16> %va, %vb
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsub_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vsub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 1 x i32> %va, %vb
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsub_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsub_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 2 x i32> %va, %vb
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsub_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsub_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 4 x i32> %va, %vb
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsub_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsub_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 8 x i32> %va, %vb
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsub_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 16 x i32> %va, %vb
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsub_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsub_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vsub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vsub_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsub_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT: vmv.v.x v25, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v25, v25, a1
+; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vsrl.vx v26, v26, a1
+; CHECK-NEXT: vor.vv v25, v26, v25
+; CHECK-NEXT: vsub.vv v16, v16, v25
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsub_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsub_vx_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 1, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vsub_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsub_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT: vmv.v.x v26, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vmv.v.x v28, a0
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vsrl.vx v28, v28, a1
+; CHECK-NEXT: vor.vv v26, v28, v26
+; CHECK-NEXT: vsub.vv v16, v16, v26
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsub_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsub_vx_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 1, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vsub_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsub_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT: vmv.v.x v28, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vor.vv v28, v8, v28
+; CHECK-NEXT: vsub.vv v16, v16, v28
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsub_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsub_vx_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 1, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vsub_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsub_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vsll.vx v24, v24, a1
+; CHECK-NEXT: vsrl.vx v24, v24, a1
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsub_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsub_vx_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll
new file mode 100644
index 000000000000..dbf4b8275983
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll
@@ -0,0 +1,777 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vsub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 1 x i8> %va, %vb
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsub_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 2 x i8> %va, %vb
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsub_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 4 x i8> %va, %vb
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsub_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 8 x i8> %va, %vb
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsub_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 16 x i8> %va, %vb
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsub_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 32 x i8> %va, %vb
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsub_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
+; CHECK-LABEL: vsub_vv_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 64 x i8> %va, %vb
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = sub <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsub_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsub_vx_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 1, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = sub <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vsub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 1 x i16> %va, %vb
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsub_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 2 x i16> %va, %vb
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsub_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 4 x i16> %va, %vb
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsub_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 8 x i16> %va, %vb
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsub_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 16 x i16> %va, %vb
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsub_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
+; CHECK-LABEL: vsub_vv_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 32 x i16> %va, %vb
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsub_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsub_vx_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 1, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = sub <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vsub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 1 x i32> %va, %vb
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsub_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 2 x i32> %va, %vb
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsub_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 4 x i32> %va, %vb
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsub_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 8 x i32> %va, %vb
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
+; CHECK-LABEL: vsub_vv_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 16 x i32> %va, %vb
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsub_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsub_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsub_vx_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 1, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = sub <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vsub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vsub_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsub_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsub_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsub_vx_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 1, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = sub <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vsub_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsub_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsub_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsub_vx_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 1, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = sub <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vsub_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsub.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsub_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsub_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsub_vx_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 1, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = sub <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vsub_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = sub <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsub_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsub_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsub_vx_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vsub.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
new file mode 100644
index 000000000000..0e0eed089a56
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
@@ -0,0 +1,1333 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vxor_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 1 x i8> %va, %vb
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vxor_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vxor_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vxor_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vxor_vi_nxv1i8_2(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 2 x i8> %va, %vb
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vi_nxv2i8_2(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 4 x i8> %va, %vb
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vi_nxv4i8_2(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 8 x i8> %va, %vb
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 16 x i8> %va, %vb
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vi_nxv16i8_2(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 32 x i8> %va, %vb
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vi_nxv32i8_2(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 64 x i8> %va, %vb
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = xor <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = xor <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv64i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = xor <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vi_nxv64i8_2(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv64i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = xor <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 1 x i16> %va, %vb
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vi_nxv1i16_2(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 2 x i16> %va, %vb
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vi_nxv2i16_2(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 4 x i16> %va, %vb
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vi_nxv4i16_2(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 8 x i16> %va, %vb
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 16 x i16> %va, %vb
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vi_nxv16i16_2(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 32 x i16> %va, %vb
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vi_nxv32i16_2(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 1 x i32> %va, %vb
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vxor_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vi_nxv1i32_2(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 2 x i32> %va, %vb
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vxor_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vi_nxv2i32_2(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 4 x i32> %va, %vb
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vxor_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vi_nxv4i32_2(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 8 x i32> %va, %vb
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vxor_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 16 x i32> %va, %vb
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vxor_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vi_nxv16i32_2(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vxor_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vxor_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT: vmv.v.x v25, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v25, v25, a1
+; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vsrl.vx v26, v26, a1
+; CHECK-NEXT: vor.vv v25, v26, v25
+; CHECK-NEXT: vxor.vv v16, v16, v25
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vi_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vxor_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vxor_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT: vmv.v.x v26, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v26, v26, a1
+; CHECK-NEXT: vmv.v.x v28, a0
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vsrl.vx v28, v28, a1
+; CHECK-NEXT: vor.vv v26, v28, v26
+; CHECK-NEXT: vxor.vv v16, v16, v26
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vi_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vxor_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vxor_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT: vmv.v.x v28, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v28, v28, a1
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vor.vv v28, v8, v28
+; CHECK-NEXT: vxor.vv v16, v16, v28
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vi_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vxor_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vxor_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: addi a1, zero, 32
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vsll.vx v24, v24, a1
+; CHECK-NEXT: vsrl.vx v24, v24, a1
+; CHECK-NEXT: vor.vv v8, v24, v8
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll
new file mode 100644
index 000000000000..2a7962ec1f41
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll
@@ -0,0 +1,1305 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vxor_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 1 x i8> %va, %vb
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vxor_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vxor_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vxor_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vxor_vi_nxv1i8_2(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i8> %va, %splat
+ ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 2 x i8> %va, %vb
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vxor_vi_nxv2i8_2(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i8> %va, %splat
+ ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 4 x i8> %va, %vb
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vxor_vi_nxv4i8_2(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i8> %va, %splat
+ ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 8 x i8> %va, %vb
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vxor_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i8> %va, %splat
+ ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 16 x i8> %va, %vb
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vxor_vi_nxv16i8_2(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i8> %va, %splat
+ ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 32 x i8> %va, %vb
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv32i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vxor_vi_nxv32i8_2(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i8> %va, %splat
+ ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
+; CHECK-LABEL: vxor_vv_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 64 x i8> %va, %vb
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv64i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = xor <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv64i8_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = xor <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv64i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 8, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = xor <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vxor_vi_nxv64i8_2(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vxor_vi_nxv64i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 64 x i8> undef, i8 16, i32 0
+ %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+ %vc = xor <vscale x 64 x i8> %va, %splat
+ ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 1 x i16> %va, %vb
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv1i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vxor_vi_nxv1i16_2(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i16> %va, %splat
+ ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 2 x i16> %va, %vb
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vxor_vi_nxv2i16_2(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i16> %va, %splat
+ ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 4 x i16> %va, %vb
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vxor_vi_nxv4i16_2(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i16> %va, %splat
+ ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 8 x i16> %va, %vb
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vxor_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i16> %va, %splat
+ ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 16 x i16> %va, %vb
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv16i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vxor_vi_nxv16i16_2(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i16> %va, %splat
+ ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
+; CHECK-LABEL: vxor_vv_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 32 x i16> %va, %vb
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv32i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i16_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 8, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vxor_vi_nxv32i16_2(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vxor_vi_nxv32i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 32 x i16> undef, i16 16, i32 0
+ %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+ %vc = xor <vscale x 32 x i16> %va, %splat
+ ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 1 x i32> %va, %vb
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vxor_vi_nxv1i32_2(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i32> %va, %splat
+ ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 2 x i32> %va, %vb
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vxor_vi_nxv2i32_2(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i32> %va, %splat
+ ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 4 x i32> %va, %vb
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vxor_vi_nxv4i32_2(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i32> %va, %splat
+ ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 8 x i32> %va, %vb
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %splat
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
+; CHECK-LABEL: vxor_vv_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 16 x i32> %va, %vb
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vxor_vx_nxv16i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 8, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vxor_vi_nxv16i32_2(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vxor_vi_nxv16i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 16 x i32> undef, i32 16, i32 0
+ %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+ %vc = xor <vscale x 16 x i32> %va, %splat
+ ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vxor_vv_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v17
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 1 x i64> %va, %vb
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vxor_vx_nxv1i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vxor_vi_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = xor <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vxor_vv_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v18
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 2 x i64> %va, %vb
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vxor_vx_nxv2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vxor_vi_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = xor <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vxor_vv_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vv v16, v16, v20
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 4 x i64> %va, %vb
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vxor_vx_nxv4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vxor_vi_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = xor <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vxor_vv_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vxor.vv v16, v16, v8
+; CHECK-NEXT: ret
+ %vc = xor <vscale x 8 x i64> %va, %vb
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vxor_vx_nxv8i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i64_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, -1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT: vxor.vi v16, v16, 8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 8, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vxor_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vxor_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT: vxor.vx v16, v16, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
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