[llvm-branch-commits] [llvm] 44ee14f - [WebAssembly][NFC] Finish cleaning up SIMD tablegen
Thomas Lively via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Dec 28 14:04:07 PST 2020
Author: Thomas Lively
Date: 2020-12-28T13:59:23-08:00
New Revision: 44ee14f993ff093c3c3ef65ab5aa1fdd3f7a1dc6
URL: https://github.com/llvm/llvm-project/commit/44ee14f993ff093c3c3ef65ab5aa1fdd3f7a1dc6
DIFF: https://github.com/llvm/llvm-project/commit/44ee14f993ff093c3c3ef65ab5aa1fdd3f7a1dc6.diff
LOG: [WebAssembly][NFC] Finish cleaning up SIMD tablegen
This commit is a follow-on to c2c2e9119e73, using the `Vec` records introduced
in that commit in the rest of the SIMD instruction definitions. Also removes
unnecessary types in output patterns.
Differential Revision: https://reviews.llvm.org/D93771
Added:
Modified:
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index df4de49ee4c8..707b7e3998d0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -37,74 +37,98 @@ def ImmI#SIZE : ImmLeaf<i32,
foreach SIZE = [2, 4, 8, 16, 32] in
def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
+// Create vector with identical lanes: splat
+def splat2 : PatFrag<(ops node:$x), (build_vector $x, $x)>;
+def splat4 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x)>;
+def splat8 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x,
+ $x, $x, $x, $x)>;
+def splat16 : PatFrag<(ops node:$x),
+ (build_vector $x, $x, $x, $x, $x, $x, $x, $x,
+ $x, $x, $x, $x, $x, $x, $x, $x)>;
+
class Vec {
ValueType vt;
+ ValueType int_vt;
ValueType lane_vt;
WebAssemblyRegClass lane_rc;
int lane_bits;
ImmLeaf lane_idx;
+ PatFrag splat;
string prefix;
Vec split;
}
def I8x16 : Vec {
let vt = v16i8;
+ let int_vt = vt;
let lane_vt = i32;
let lane_rc = I32;
let lane_bits = 8;
let lane_idx = LaneIdx16;
+ let splat = splat16;
let prefix = "i8x16";
}
def I16x8 : Vec {
let vt = v8i16;
+ let int_vt = vt;
let lane_vt = i32;
let lane_rc = I32;
let lane_bits = 16;
let lane_idx = LaneIdx8;
+ let splat = splat8;
let prefix = "i16x8";
let split = I8x16;
}
def I32x4 : Vec {
let vt = v4i32;
+ let int_vt = vt;
let lane_vt = i32;
let lane_rc = I32;
let lane_bits = 32;
let lane_idx = LaneIdx4;
+ let splat = splat4;
let prefix = "i32x4";
let split = I16x8;
}
def I64x2 : Vec {
let vt = v2i64;
+ let int_vt = vt;
let lane_vt = i64;
let lane_rc = I64;
let lane_bits = 64;
let lane_idx = LaneIdx2;
+ let splat = splat2;
let prefix = "i64x2";
let split = I32x4;
}
def F32x4 : Vec {
let vt = v4f32;
+ let int_vt = v4i32;
let lane_vt = f32;
let lane_rc = F32;
let lane_bits = 32;
let lane_idx = LaneIdx4;
+ let splat = splat4;
let prefix = "f32x4";
}
def F64x2 : Vec {
let vt = v2f64;
+ let int_vt = v2i64;
let lane_vt = f64;
let lane_rc = F64;
let lane_bits = 64;
let lane_idx = LaneIdx2;
+ let splat = splat2;
let prefix = "f64x2";
}
defvar AllVecs = [I8x16, I16x8, I32x4, I64x2, F32x4, F64x2];
+defvar IntVecs = [I8x16, I16x8, I32x4, I64x2];
//===----------------------------------------------------------------------===//
// Load and store
@@ -289,11 +313,11 @@ multiclass LoadLanePatNoOffset<Vec vec, PatFrag kind> {
defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64");
def : Pat<(vec.vt (kind (i32 I32:$addr),
(vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
- (load_lane_a32 0, 0, imm:$idx, I32:$addr, V128:$vec)>,
+ (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
Requires<[HasAddr32]>;
def : Pat<(vec.vt (kind (i64 I64:$addr),
(vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
- (load_lane_a64 0, 0, imm:$idx, I64:$addr, V128:$vec)>,
+ (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>,
Requires<[HasAddr64]>;
}
@@ -359,12 +383,10 @@ defm "" : SIMDStoreLane<I64x2, 95>;
// Select stores with no constant offset.
multiclass StoreLanePatNoOffset<Vec vec, PatFrag kind> {
def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
- (!cast<NI>("STORE_LANE_"#vec#"_A32")
- 0, 0, imm:$idx, I32:$addr, vec.vt:$vec)>,
+ (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>,
Requires<[HasAddr32]>;
def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
- (!cast<NI>("STORE_LANE_"#vec#"_A64")
- 0, 0, imm:$idx, I64:$addr, vec.vt:$vec)>,
+ (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, 0, imm:$idx, $addr, $vec)>,
Requires<[HasAddr64]>;
}
@@ -381,16 +403,16 @@ defm : StoreLanePatNoOffset<I64x2, int_wasm_store64_lane>;
//===----------------------------------------------------------------------===//
// Constant: v128.const
-multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
+multiclass ConstVec<Vec vec, dag ops, dag pat, string args> {
let isMoveImm = 1, isReMaterializable = 1,
Predicates = [HasUnimplementedSIMD128] in
- defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
- [(set V128:$dst, (vec_t pat))],
- "v128.const\t$dst, "#args,
- "v128.const\t"#args, 12>;
+ defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops,
+ [(set V128:$dst, (vec.vt pat))],
+ "v128.const\t$dst, "#args,
+ "v128.const\t"#args, 12>;
}
-defm "" : ConstVec<v16i8,
+defm "" : ConstVec<I8x16,
(ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
vec_i8imm_op:$i2, vec_i8imm_op:$i3,
vec_i8imm_op:$i4, vec_i8imm_op:$i5,
@@ -405,7 +427,7 @@ defm "" : ConstVec<v16i8,
ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
!strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
"$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
-defm "" : ConstVec<v8i16,
+defm "" : ConstVec<I16x8,
(ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
vec_i16imm_op:$i2, vec_i16imm_op:$i3,
vec_i16imm_op:$i4, vec_i16imm_op:$i5,
@@ -415,23 +437,23 @@ defm "" : ConstVec<v8i16,
ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
"$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
let IsCanonical = 1 in
-defm "" : ConstVec<v4i32,
+defm "" : ConstVec<I32x4,
(ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
vec_i32imm_op:$i2, vec_i32imm_op:$i3),
(build_vector (i32 imm:$i0), (i32 imm:$i1),
(i32 imm:$i2), (i32 imm:$i3)),
"$i0, $i1, $i2, $i3">;
-defm "" : ConstVec<v2i64,
+defm "" : ConstVec<I64x2,
(ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
(build_vector (i64 imm:$i0), (i64 imm:$i1)),
"$i0, $i1">;
-defm "" : ConstVec<v4f32,
+defm "" : ConstVec<F32x4,
(ins f32imm_op:$i0, f32imm_op:$i1,
f32imm_op:$i2, f32imm_op:$i3),
(build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
(f32 fpimm:$i2), (f32 fpimm:$i3)),
"$i0, $i1, $i2, $i3">;
-defm "" : ConstVec<v2f64,
+defm "" : ConstVec<F64x2,
(ins f64imm_op:$i0, f64imm_op:$i1),
(build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
"$i0, $i1">;
@@ -470,8 +492,8 @@ defm SHUFFLE :
// Shuffles after custom lowering
def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
-foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
-def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
+foreach vec = AllVecs in {
+def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
(i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
(i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
(i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
@@ -480,15 +502,11 @@ def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
(i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
(i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
(i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
- (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y),
- (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
- (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
- (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
- (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
- (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
- (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
- (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
- (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
+ (SHUFFLE $x, $y,
+ imm:$m0, imm:$m1, imm:$m2, imm:$m3,
+ imm:$m4, imm:$m5, imm:$m6, imm:$m7,
+ imm:$m8, imm:$m9, imm:$mA, imm:$mB,
+ imm:$mC, imm:$mD, imm:$mE, imm:$mF)>;
}
// Swizzle lanes: i8x16.swizzle
@@ -501,157 +519,133 @@ defm SWIZZLE :
"i8x16.swizzle\t$dst, $src, $mask", "i8x16.swizzle", 14>;
def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
- (SWIZZLE V128:$src, V128:$mask)>;
-
-// Create vector with identical lanes: splat
-def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
-def splat4 : PatFrag<(ops node:$x), (build_vector
- node:$x, node:$x, node:$x, node:$x)>;
-def splat8 : PatFrag<(ops node:$x), (build_vector
- node:$x, node:$x, node:$x, node:$x,
- node:$x, node:$x, node:$x, node:$x)>;
-def splat16 : PatFrag<(ops node:$x), (build_vector
- node:$x, node:$x, node:$x, node:$x,
- node:$x, node:$x, node:$x, node:$x,
- node:$x, node:$x, node:$x, node:$x,
- node:$x, node:$x, node:$x, node:$x)>;
-
-multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
- PatFrag splat_pat, bits<32> simdop> {
- defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
- [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
- vec#".splat\t$dst, $x", vec#".splat", simdop>;
+ (SWIZZLE $src, $mask)>;
+
+multiclass Splat<Vec vec, bits<32> simdop> {
+ defm SPLAT_#vec : SIMD_I<(outs V128:$dst), (ins vec.lane_rc:$x),
+ (outs), (ins),
+ [(set (vec.vt V128:$dst),
+ (vec.splat vec.lane_rc:$x))],
+ vec.prefix#".splat\t$dst, $x", vec.prefix#".splat",
+ simdop>;
}
-defm "" : Splat<v16i8, "i8x16", I32, splat16, 15>;
-defm "" : Splat<v8i16, "i16x8", I32, splat8, 16>;
-defm "" : Splat<v4i32, "i32x4", I32, splat4, 17>;
-defm "" : Splat<v2i64, "i64x2", I64, splat2, 18>;
-defm "" : Splat<v4f32, "f32x4", F32, splat4, 19>;
-defm "" : Splat<v2f64, "f64x2", F64, splat2, 20>;
+defm "" : Splat<I8x16, 15>;
+defm "" : Splat<I16x8, 16>;
+defm "" : Splat<I32x4, 17>;
+defm "" : Splat<I64x2, 18>;
+defm "" : Splat<F32x4, 19>;
+defm "" : Splat<F64x2, 20>;
// scalar_to_vector leaves high lanes undefined, so can be a splat
-class ScalarSplatPat<ValueType vec_t, ValueType lane_t,
- WebAssemblyRegClass reg_t> :
- Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))),
- (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>;
-
-def : ScalarSplatPat<v16i8, i32, I32>;
-def : ScalarSplatPat<v8i16, i32, I32>;
-def : ScalarSplatPat<v4i32, i32, I32>;
-def : ScalarSplatPat<v2i64, i64, I64>;
-def : ScalarSplatPat<v4f32, f32, F32>;
-def : ScalarSplatPat<v2f64, f64, F64>;
+foreach vec = AllVecs in
+def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))),
+ (!cast<Instruction>("SPLAT_"#vec) $x)>;
//===----------------------------------------------------------------------===//
// Accessing lanes
//===----------------------------------------------------------------------===//
// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u
-multiclass ExtractLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
- bits<32> simdop, string suffix = ""> {
- defm EXTRACT_LANE_#vec_t#suffix :
- SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
+multiclass ExtractLane<Vec vec, bits<32> simdop, string suffix = ""> {
+ defm EXTRACT_LANE_#vec#suffix :
+ SIMD_I<(outs vec.lane_rc:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
(outs), (ins vec_i8imm_op:$idx), [],
- vec#".extract_lane"#suffix#"\t$dst, $vec, $idx",
- vec#".extract_lane"#suffix#"\t$idx", simdop>;
+ vec.prefix#".extract_lane"#suffix#"\t$dst, $vec, $idx",
+ vec.prefix#".extract_lane"#suffix#"\t$idx", simdop>;
}
-defm "" : ExtractLane<v16i8, "i8x16", I32, 21, "_s">;
-defm "" : ExtractLane<v16i8, "i8x16", I32, 22, "_u">;
-defm "" : ExtractLane<v8i16, "i16x8", I32, 24, "_s">;
-defm "" : ExtractLane<v8i16, "i16x8", I32, 25, "_u">;
-defm "" : ExtractLane<v4i32, "i32x4", I32, 27>;
-defm "" : ExtractLane<v2i64, "i64x2", I64, 29>;
-defm "" : ExtractLane<v4f32, "f32x4", F32, 31>;
-defm "" : ExtractLane<v2f64, "f64x2", F64, 33>;
+defm "" : ExtractLane<I8x16, 21, "_s">;
+defm "" : ExtractLane<I8x16, 22, "_u">;
+defm "" : ExtractLane<I16x8, 24, "_s">;
+defm "" : ExtractLane<I16x8, 25, "_u">;
+defm "" : ExtractLane<I32x4, 27>;
+defm "" : ExtractLane<I64x2, 29>;
+defm "" : ExtractLane<F32x4, 31>;
+defm "" : ExtractLane<F64x2, 33>;
def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)),
- (EXTRACT_LANE_v16i8_u V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)),
- (EXTRACT_LANE_v8i16_u V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)),
- (EXTRACT_LANE_v4i32 V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_I32x4 $vec, imm:$idx)>;
def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)),
- (EXTRACT_LANE_v4f32 V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_F32x4 $vec, imm:$idx)>;
def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)),
- (EXTRACT_LANE_v2i64 V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_I64x2 $vec, imm:$idx)>;
def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)),
- (EXTRACT_LANE_v2f64 V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_F64x2 $vec, imm:$idx)>;
def : Pat<
(sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8),
- (EXTRACT_LANE_v16i8_s V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_I8x16_s $vec, imm:$idx)>;
def : Pat<
(and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)),
- (EXTRACT_LANE_v16i8_u V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
def : Pat<
(sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16),
- (EXTRACT_LANE_v8i16_s V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_I16x8_s $vec, imm:$idx)>;
def : Pat<
(and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)),
- (EXTRACT_LANE_v8i16_u V128:$vec, imm:$idx)>;
+ (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
// Replace lane value: replace_lane
-multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
- WebAssemblyRegClass reg_t, ValueType lane_t,
- bits<32> simdop> {
- defm REPLACE_LANE_#vec_t :
- SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x),
- (outs), (ins vec_i8imm_op:$idx),
- [(set V128:$dst, (vector_insert
- (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
- vec#".replace_lane\t$dst, $vec, $idx, $x",
- vec#".replace_lane\t$idx", simdop>;
+multiclass ReplaceLane<Vec vec, bits<32> simdop> {
+ defm REPLACE_LANE_#vec :
+ SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, vec.lane_rc:$x),
+ (outs), (ins vec_i8imm_op:$idx),
+ [(set V128:$dst, (vector_insert
+ (vec.vt V128:$vec),
+ (vec.lane_vt vec.lane_rc:$x),
+ (i32 vec.lane_idx:$idx)))],
+ vec.prefix#".replace_lane\t$dst, $vec, $idx, $x",
+ vec.prefix#".replace_lane\t$idx", simdop>;
}
-defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 23>;
-defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 26>;
-defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 28>;
-defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 30>;
-defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 32>;
-defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 34>;
+defm "" : ReplaceLane<I8x16, 23>;
+defm "" : ReplaceLane<I16x8, 26>;
+defm "" : ReplaceLane<I32x4, 28>;
+defm "" : ReplaceLane<I64x2, 30>;
+defm "" : ReplaceLane<F32x4, 32>;
+defm "" : ReplaceLane<F64x2, 34>;
// Lower undef lane indices to zero
def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
- (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>;
+ (REPLACE_LANE_I8x16 $vec, 0, $x)>;
def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
- (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>;
+ (REPLACE_LANE_I16x8 $vec, 0, $x)>;
def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
- (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>;
+ (REPLACE_LANE_I32x4 $vec, 0, $x)>;
def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
- (REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>;
+ (REPLACE_LANE_I64x2 $vec, 0, $x)>;
def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
- (REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>;
+ (REPLACE_LANE_F32x4 $vec, 0, $x)>;
def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
- (REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>;
+ (REPLACE_LANE_F64x2 $vec, 0, $x)>;
//===----------------------------------------------------------------------===//
// Comparisons
//===----------------------------------------------------------------------===//
-multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
- string name, CondCode cond, bits<32> simdop> {
- defm _#vec_t :
+multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> {
+ defm _#vec :
SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
- [(set (out_t V128:$dst),
- (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
- )],
- vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
+ [(set (vec.int_vt V128:$dst),
+ (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))],
+ vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
+ vec.prefix#"."#name, simdop>;
}
multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
- defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
- defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
- !add(baseInst, 10)>;
- defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
- !add(baseInst, 20)>;
+ defm "" : SIMDCondition<I8x16, name, cond, baseInst>;
+ defm "" : SIMDCondition<I16x8, name, cond, !add(baseInst, 10)>;
+ defm "" : SIMDCondition<I32x4, name, cond, !add(baseInst, 20)>;
}
multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
- defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
- defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
- !add(baseInst, 6)>;
+ defm "" : SIMDCondition<F32x4, name, cond, baseInst>;
+ defm "" : SIMDCondition<F64x2, name, cond, !add(baseInst, 6)>;
}
// Equality: eq
@@ -689,22 +683,21 @@ defm GE : SIMDConditionFP<"ge", SETOGE, 70>;
// Lower float comparisons that don't care about NaN to standard WebAssembly
// float comparisons. These instructions are generated with nnan and in the
// target-independent expansion of unordered comparisons and ordered ne.
-foreach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32],
- [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in
+foreach nodes = [[seteq, EQ_F32x4], [setne, NE_F32x4], [setlt, LT_F32x4],
+ [setgt, GT_F32x4], [setle, LE_F32x4], [setge, GE_F32x4]] in
def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
- (v4i32 (nodes[1] (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
+ (nodes[1] $lhs, $rhs)>;
-foreach nodes = [[seteq, EQ_v2f64], [setne, NE_v2f64], [setlt, LT_v2f64],
- [setgt, GT_v2f64], [setle, LE_v2f64], [setge, GE_v2f64]] in
+foreach nodes = [[seteq, EQ_F64x2], [setne, NE_F64x2], [setlt, LT_F64x2],
+ [setgt, GT_F64x2], [setle, LE_F64x2], [setge, GE_F64x2]] in
def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
- (v2i64 (nodes[1] (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
+ (nodes[1] $lhs, $rhs)>;
// Prototype i64x2.eq
defm EQ_v2i64 :
SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
[(set (v2i64 V128:$dst),
- (int_wasm_eq (v2i64 V128:$lhs), (v2i64 V128:$rhs))
- )],
+ (int_wasm_eq (v2i64 V128:$lhs), (v2i64 V128:$rhs)))],
"i64x2.eq\t$dst, $lhs, $rhs", "i64x2.eq", 192>;
@@ -712,151 +705,135 @@ defm EQ_v2i64 :
// Bitwise operations
//===----------------------------------------------------------------------===//
-multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name,
- bits<32> simdop> {
- defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
- (outs), (ins),
- [(set (vec_t V128:$dst),
- (node (vec_t V128:$lhs), (vec_t V128:$rhs))
- )],
- vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
- simdop>;
+multiclass SIMDBinary<Vec vec, SDNode node, string name, bits<32> simdop> {
+ defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
+ (outs), (ins),
+ [(set (vec.vt V128:$dst),
+ (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
+ vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
+ vec.prefix#"."#name, simdop>;
}
-multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
- defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
- defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
- defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
- defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
+multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop, bit commutable = false> {
+ let isCommutable = commutable in
+ defm "" : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
+ (outs), (ins), [],
+ "v128."#name#"\t$dst, $lhs, $rhs", "v128."#name, simdop>;
+ foreach vec = IntVecs in
+ def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
+ (!cast<NI>(NAME) $lhs, $rhs)>;
}
-multiclass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name,
- bits<32> simdop> {
- defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
- [(set (vec_t V128:$dst),
- (vec_t (node (vec_t V128:$vec)))
- )],
- vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
+multiclass SIMDUnary<Vec vec, SDNode node, string name, bits<32> simdop> {
+ defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins),
+ [(set (vec.vt V128:$dst),
+ (vec.vt (node (vec.vt V128:$v))))],
+ vec.prefix#"."#name#"\t$dst, $v",
+ vec.prefix#"."#name, simdop>;
}
// Bitwise logic: v128.not
-foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
-defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 77>;
+defm NOT : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins), [],
+ "v128.not\t$dst, $v", "v128.not", 77>;
+foreach vec = IntVecs in
+def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>;
// Bitwise logic: v128.and / v128.or / v128.xor
-let isCommutable = 1 in {
-defm AND : SIMDBitwise<and, "and", 78>;
-defm OR : SIMDBitwise<or, "or", 80>;
-defm XOR : SIMDBitwise<xor, "xor", 81>;
-} // isCommutable = 1
+defm AND : SIMDBitwise<and, "and", 78, true>;
+defm OR : SIMDBitwise<or, "or", 80, true>;
+defm XOR : SIMDBitwise<xor, "xor", 81, true>;
// Bitwise logic: v128.andnot
def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>;
defm ANDNOT : SIMDBitwise<andnot, "andnot", 79>;
// Bitwise select: v128.bitselect
-foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
- defm BITSELECT_#vec_t :
- SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
- [(set (vec_t V128:$dst),
- (vec_t (int_wasm_bitselect
- (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
- ))
- )],
- "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>;
+defm BITSELECT :
+ SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), [],
+ "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>;
+
+foreach vec = AllVecs in
+def : Pat<(vec.vt (int_wasm_bitselect
+ (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))),
+ (BITSELECT $v1, $v2, $c)>;
// Bitselect is equivalent to (c & v1) | (~c & v2)
-foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
- def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
- (and (vnot V128:$c), (vec_t V128:$v2)))),
- (!cast<Instruction>("BITSELECT_"#vec_t)
- V128:$v1, V128:$v2, V128:$c)>;
+foreach vec = IntVecs in
+def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)),
+ (and (vnot V128:$c), (vec.vt V128:$v2)))),
+ (BITSELECT $v1, $v2, $c)>;
// Also implement vselect in terms of bitselect
-foreach types = [[v16i8, v16i8], [v8i16, v8i16], [v4i32, v4i32], [v2i64, v2i64],
- [v4f32, v4i32], [v2f64, v2i64]] in
- def : Pat<(types[0] (vselect
- (types[1] V128:$c), (types[0] V128:$v1), (types[0] V128:$v2)
- )),
- (!cast<Instruction>("BITSELECT_"#types[0])
- V128:$v1, V128:$v2, V128:$c
- )>;
+foreach vec = AllVecs in
+def : Pat<(vec.vt (vselect
+ (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))),
+ (BITSELECT $v1, $v2, $c)>;
// MVP select on v128 values
-foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
-defm SELECT_#vec_t : I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond),
- (outs), (ins),
- [(set V128:$dst,
- (select I32:$cond,
- (vec_t V128:$lhs), (vec_t V128:$rhs)
- )
- )],
- "v128.select\t$dst, $lhs, $rhs, $cond",
- "v128.select", 0x1b>;
+defm SELECT_V128 :
+ I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond), (outs), (ins), [],
+ "v128.select\t$dst, $lhs, $rhs, $cond", "v128.select", 0x1b>;
+
+foreach vec = AllVecs in {
+def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
+ (SELECT_V128 $lhs, $rhs, $cond)>;
// ISD::SELECT requires its operand to conform to getBooleanContents, but
// WebAssembly's select interprets any non-zero value as true, so we can fold
// a setne with 0 into a select.
def : Pat<(select
- (i32 (setne I32:$cond, 0)), (vec_t V128:$lhs), (vec_t V128:$rhs)
- ),
- (!cast<Instruction>("SELECT_"#vec_t)
- V128:$lhs, V128:$rhs, I32:$cond
- )>;
+ (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
+ (SELECT_V128 $lhs, $rhs, $cond)>;
// And again, this time with seteq instead of setne and the arms reversed.
def : Pat<(select
- (i32 (seteq I32:$cond, 0)), (vec_t V128:$lhs), (vec_t V128:$rhs)
- ),
- (!cast<Instruction>("SELECT_"#vec_t)
- V128:$rhs, V128:$lhs, I32:$cond
- )>;
-} // foreach vec_t
+ (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
+ (SELECT_V128 $rhs, $lhs, $cond)>;
+} // foreach vec
// Sign select
-multiclass SIMDSignSelect<ValueType vec_t, string vec, bits<32> simdop> {
- defm SIGNSELECT_#vec_t :
+multiclass SIMDSignSelect<Vec vec, bits<32> simdop> {
+ defm SIGNSELECT_#vec :
SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
- [(set (vec_t V128:$dst),
- (vec_t (int_wasm_signselect
- (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
- ))
- )],
- vec#".signselect\t$dst, $v1, $v2, $c", vec#".signselect", simdop>;
+ [(set (vec.vt V128:$dst),
+ (vec.vt (int_wasm_signselect
+ (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))))],
+ vec.prefix#".signselect\t$dst, $v1, $v2, $c",
+ vec.prefix#".signselect", simdop>;
}
-defm : SIMDSignSelect<v16i8, "i8x16", 125>;
-defm : SIMDSignSelect<v8i16, "i16x8", 126>;
-defm : SIMDSignSelect<v4i32, "i32x4", 127>;
-defm : SIMDSignSelect<v2i64, "i64x2", 148>;
+defm : SIMDSignSelect<I8x16, 125>;
+defm : SIMDSignSelect<I16x8, 126>;
+defm : SIMDSignSelect<I32x4, 127>;
+defm : SIMDSignSelect<I64x2, 148>;
//===----------------------------------------------------------------------===//
// Integer unary arithmetic
//===----------------------------------------------------------------------===//
multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> {
- defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>;
- defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 32)>;
- defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 64)>;
- defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 96)>;
+ defm "" : SIMDUnary<I8x16, node, name, baseInst>;
+ defm "" : SIMDUnary<I16x8, node, name, !add(baseInst, 32)>;
+ defm "" : SIMDUnary<I32x4, node, name, !add(baseInst, 64)>;
+ defm "" : SIMDUnary<I64x2, node, name, !add(baseInst, 96)>;
}
-multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name,
- bits<32> simdop> {
- defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
- [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
- vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
+multiclass SIMDReduceVec<Vec vec, SDNode op, string name, bits<32> simdop> {
+ defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
+ [(set I32:$dst, (i32 (op (vec.vt V128:$vec))))],
+ vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name,
+ simdop>;
}
multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
- defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>;
- defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 32)>;
- defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 64)>;
- defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 96)>;
+ defm "" : SIMDReduceVec<I8x16, op, name, baseInst>;
+ defm "" : SIMDReduceVec<I16x8, op, name, !add(baseInst, 32)>;
+ defm "" : SIMDReduceVec<I32x4, op, name, !add(baseInst, 64)>;
+ defm "" : SIMDReduceVec<I64x2, op, name, !add(baseInst, 96)>;
}
// Integer vector negation
-def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
+def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, $in)>;
// Integer absolute value: abs
defm ABS : SIMDUnaryInt<abs, "abs", 96>;
@@ -871,67 +848,55 @@ defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 98>;
defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 99>;
// Population count: popcnt
-defm POPCNT : SIMDUnary<v16i8, "i8x16", int_wasm_popcnt, "popcnt", 124>;
+defm POPCNT : SIMDUnary<I8x16, int_wasm_popcnt, "popcnt", 124>;
// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
// can be folded out
foreach reduction =
[["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in
-foreach ty = [v16i8, v8i16, v4i32, v2i64] in {
-def : Pat<(i32 (and
- (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
- (i32 1)
- )),
- (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
-def : Pat<(i32 (setne
- (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
- (i32 0)
- )),
- (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
-def : Pat<(i32 (seteq
- (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
- (i32 1)
- )),
- (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
+foreach vec = IntVecs in {
+defvar intrinsic = !cast<Intrinsic>(reduction[0]);
+defvar inst = !cast<NI>(reduction[1]#"_"#vec);
+def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
+def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
+def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
}
-multiclass SIMDBitmask<ValueType vec_t, string vec, bits<32> simdop> {
- defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
- [(set I32:$dst,
- (i32 (int_wasm_bitmask (vec_t V128:$vec)))
- )],
- vec#".bitmask\t$dst, $vec", vec#".bitmask", simdop>;
+multiclass SIMDBitmask<Vec vec, bits<32> simdop> {
+ defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
+ [(set I32:$dst,
+ (i32 (int_wasm_bitmask (vec.vt V128:$vec))))],
+ vec.prefix#".bitmask\t$dst, $vec", vec.prefix#".bitmask",
+ simdop>;
}
-defm BITMASK : SIMDBitmask<v16i8, "i8x16", 100>;
-defm BITMASK : SIMDBitmask<v8i16, "i16x8", 132>;
-defm BITMASK : SIMDBitmask<v4i32, "i32x4", 164>;
-defm BITMASK : SIMDBitmask<v2i64, "i64x2", 196>;
+defm BITMASK : SIMDBitmask<I8x16, 100>;
+defm BITMASK : SIMDBitmask<I16x8, 132>;
+defm BITMASK : SIMDBitmask<I32x4, 164>;
+defm BITMASK : SIMDBitmask<I64x2, 196>;
//===----------------------------------------------------------------------===//
// Bit shifts
//===----------------------------------------------------------------------===//
-multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, string name,
- bits<32> simdop> {
- defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x),
- (outs), (ins),
- [(set (vec_t V128:$dst), (node V128:$vec, I32:$x))],
- vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>;
+multiclass SIMDShift<Vec vec, SDNode node, string name, bits<32> simdop> {
+ defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), (outs), (ins),
+ [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))],
+ vec.prefix#"."#name#"\t$dst, $vec, $x",
+ vec.prefix#"."#name, simdop>;
}
multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> {
- defm "" : SIMDShift<v16i8, "i8x16", node, name, baseInst>;
- defm "" : SIMDShift<v8i16, "i16x8", node, name, !add(baseInst, 32)>;
- defm "" : SIMDShift<v4i32, "i32x4", node, name, !add(baseInst, 64)>;
- defm "" : SIMDShift<v2i64, "i64x2", node, name, !add(baseInst, 96)>;
+ defm "" : SIMDShift<I8x16, node, name, baseInst>;
+ defm "" : SIMDShift<I16x8, node, name, !add(baseInst, 32)>;
+ defm "" : SIMDShift<I32x4, node, name, !add(baseInst, 64)>;
+ defm "" : SIMDShift<I64x2, node, name, !add(baseInst, 96)>;
}
// WebAssembly SIMD shifts are nonstandard in that the shift amount is
// an i32 rather than a vector, so they need custom nodes.
-def wasm_shift_t : SDTypeProfile<1, 2,
- [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]
->;
+def wasm_shift_t :
+ SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>;
def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>;
def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>;
@@ -948,24 +913,24 @@ defm SHR_U : SIMDShiftInt<wasm_shr_u, "shr_u", 109>;
//===----------------------------------------------------------------------===//
multiclass SIMDBinaryIntNoI8x16<SDNode node, string name, bits<32> baseInst> {
- defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>;
- defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>;
- defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>;
+ defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>;
+ defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>;
+ defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>;
}
multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
- defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
- defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>;
+ defm "" : SIMDBinary<I8x16, node, name, baseInst>;
+ defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>;
}
multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
- defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>;
+ defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>;
}
multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
- defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>;
+ defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>;
}
// Integer addition: add / add_saturate_s / add_saturate_u
@@ -996,23 +961,22 @@ defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>;
// Integer unsigned rounding average: avgr_u
let isCommutable = 1 in {
-defm AVGR_U : SIMDBinary<v16i8, "i8x16", int_wasm_avgr_unsigned, "avgr_u", 123>;
-defm AVGR_U : SIMDBinary<v8i16, "i16x8", int_wasm_avgr_unsigned, "avgr_u", 155>;
+defm AVGR_U : SIMDBinary<I8x16, int_wasm_avgr_unsigned, "avgr_u", 123>;
+defm AVGR_U : SIMDBinary<I16x8, int_wasm_avgr_unsigned, "avgr_u", 155>;
}
-def add_nuw : PatFrag<(ops node:$lhs, node:$rhs),
- (add node:$lhs, node:$rhs),
+def add_nuw : PatFrag<(ops node:$lhs, node:$rhs), (add $lhs, $rhs),
"return N->getFlags().hasNoUnsignedWrap();">;
-foreach nodes = [[v16i8, splat16], [v8i16, splat8]] in
+foreach vec = [I8x16, I16x8] in {
+defvar inst = !cast<NI>("AVGR_U_"#vec);
def : Pat<(wasm_shr_u
(add_nuw
- (add_nuw (nodes[0] V128:$lhs), (nodes[0] V128:$rhs)),
- (nodes[1] (i32 1))
- ),
- (i32 1)
- ),
- (!cast<NI>("AVGR_U_"#nodes[0]) V128:$lhs, V128:$rhs)>;
+ (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
+ (vec.splat (i32 1))),
+ (i32 1)),
+ (inst $lhs, $rhs)>;
+}
// Widening dot product: i32x4.dot_i16x8_s
let isCommutable = 1 in
@@ -1022,63 +986,49 @@ defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
186>;
// Extending multiplication: extmul_{low,high}_P, extmul_high
-multiclass SIMDExtBinary<ValueType vec_t, ValueType arg_t, string vec,
- SDNode node, string name, bits<32> simdop> {
- defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
- (outs), (ins),
- [(set (vec_t V128:$dst),
- (node (arg_t V128:$lhs), (arg_t V128:$rhs))
- )],
- vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
- simdop>;
+multiclass SIMDExtBinary<Vec vec, SDNode node, string name, bits<32> simdop> {
+ defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
+ (outs), (ins),
+ [(set (vec.vt V128:$dst), (node
+ (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))],
+ vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
+ vec.prefix#"."#name, simdop>;
}
defm EXTMUL_LOW_S :
- SIMDExtBinary<v8i16, v16i8, "i16x8", int_wasm_extmul_low_signed,
- "extmul_low_i8x16_s", 154>;
+ SIMDExtBinary<I16x8, int_wasm_extmul_low_signed, "extmul_low_i8x16_s", 154>;
defm EXTMUL_HIGH_S :
- SIMDExtBinary<v8i16, v16i8, "i16x8", int_wasm_extmul_high_signed,
- "extmul_high_i8x16_s", 157>;
+ SIMDExtBinary<I16x8, int_wasm_extmul_high_signed, "extmul_high_i8x16_s", 157>;
defm EXTMUL_LOW_U :
- SIMDExtBinary<v8i16, v16i8, "i16x8", int_wasm_extmul_low_unsigned,
- "extmul_low_i8x16_u", 158>;
+ SIMDExtBinary<I16x8, int_wasm_extmul_low_unsigned, "extmul_low_i8x16_u", 158>;
defm EXTMUL_HIGH_U :
- SIMDExtBinary<v8i16, v16i8, "i16x8", int_wasm_extmul_high_unsigned,
- "extmul_high_i8x16_u", 159>;
+ SIMDExtBinary<I16x8, int_wasm_extmul_high_unsigned, "extmul_high_i8x16_u", 159>;
defm EXTMUL_LOW_S :
- SIMDExtBinary<v4i32, v8i16, "i32x4", int_wasm_extmul_low_signed,
- "extmul_low_i16x8_s", 187>;
+ SIMDExtBinary<I32x4, int_wasm_extmul_low_signed, "extmul_low_i16x8_s", 187>;
defm EXTMUL_HIGH_S :
- SIMDExtBinary<v4i32, v8i16, "i32x4", int_wasm_extmul_high_signed,
- "extmul_high_i16x8_s", 189>;
+ SIMDExtBinary<I32x4, int_wasm_extmul_high_signed, "extmul_high_i16x8_s", 189>;
defm EXTMUL_LOW_U :
- SIMDExtBinary<v4i32, v8i16, "i32x4", int_wasm_extmul_low_unsigned,
- "extmul_low_i16x8_u", 190>;
+ SIMDExtBinary<I32x4, int_wasm_extmul_low_unsigned, "extmul_low_i16x8_u", 190>;
defm EXTMUL_HIGH_U :
- SIMDExtBinary<v4i32, v8i16, "i32x4", int_wasm_extmul_high_unsigned,
- "extmul_high_i16x8_u", 191>;
+ SIMDExtBinary<I32x4, int_wasm_extmul_high_unsigned, "extmul_high_i16x8_u", 191>;
defm EXTMUL_LOW_S :
- SIMDExtBinary<v2i64, v4i32, "i64x2", int_wasm_extmul_low_signed,
- "extmul_low_i32x4_s", 210>;
+ SIMDExtBinary<I64x2, int_wasm_extmul_low_signed, "extmul_low_i32x4_s", 210>;
defm EXTMUL_HIGH_S :
- SIMDExtBinary<v2i64, v4i32, "i64x2", int_wasm_extmul_high_signed,
- "extmul_high_i32x4_s", 211>;
+ SIMDExtBinary<I64x2, int_wasm_extmul_high_signed, "extmul_high_i32x4_s", 211>;
defm EXTMUL_LOW_U :
- SIMDExtBinary<v2i64, v4i32, "i64x2", int_wasm_extmul_low_unsigned,
- "extmul_low_i32x4_u", 214>;
+ SIMDExtBinary<I64x2, int_wasm_extmul_low_unsigned, "extmul_low_i32x4_u", 214>;
defm EXTMUL_HIGH_U :
- SIMDExtBinary<v2i64, v4i32, "i64x2", int_wasm_extmul_high_unsigned,
- "extmul_high_i32x4_u", 215>;
+ SIMDExtBinary<I64x2, int_wasm_extmul_high_unsigned, "extmul_high_i32x4_u", 215>;
//===----------------------------------------------------------------------===//
// Floating-point unary arithmetic
//===----------------------------------------------------------------------===//
multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
- defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>;
- defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 12)>;
+ defm "" : SIMDUnary<F32x4, node, name, baseInst>;
+ defm "" : SIMDUnary<F64x2, node, name, !add(baseInst, 12)>;
}
// Absolute value: abs
@@ -1091,22 +1041,22 @@ defm NEG : SIMDUnaryFP<fneg, "neg", 225>;
defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>;
// Rounding: ceil, floor, trunc, nearest
-defm CEIL : SIMDUnary<v4f32, "f32x4", int_wasm_ceil, "ceil", 216>;
-defm FLOOR : SIMDUnary<v4f32, "f32x4", int_wasm_floor, "floor", 217>;
-defm TRUNC: SIMDUnary<v4f32, "f32x4", int_wasm_trunc, "trunc", 218>;
-defm NEAREST: SIMDUnary<v4f32, "f32x4", int_wasm_nearest, "nearest", 219>;
-defm CEIL : SIMDUnary<v2f64, "f64x2", int_wasm_ceil, "ceil", 220>;
-defm FLOOR : SIMDUnary<v2f64, "f64x2", int_wasm_floor, "floor", 221>;
-defm TRUNC: SIMDUnary<v2f64, "f64x2", int_wasm_trunc, "trunc", 222>;
-defm NEAREST: SIMDUnary<v2f64, "f64x2", int_wasm_nearest, "nearest", 223>;
+defm CEIL : SIMDUnary<F32x4, int_wasm_ceil, "ceil", 216>;
+defm FLOOR : SIMDUnary<F32x4, int_wasm_floor, "floor", 217>;
+defm TRUNC: SIMDUnary<F32x4, int_wasm_trunc, "trunc", 218>;
+defm NEAREST: SIMDUnary<F32x4, int_wasm_nearest, "nearest", 219>;
+defm CEIL : SIMDUnary<F64x2, int_wasm_ceil, "ceil", 220>;
+defm FLOOR : SIMDUnary<F64x2, int_wasm_floor, "floor", 221>;
+defm TRUNC: SIMDUnary<F64x2, int_wasm_trunc, "trunc", 222>;
+defm NEAREST: SIMDUnary<F64x2, int_wasm_nearest, "nearest", 223>;
//===----------------------------------------------------------------------===//
// Floating-point binary arithmetic
//===----------------------------------------------------------------------===//
multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
- defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
- defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 12)>;
+ defm "" : SIMDBinary<F32x4, node, name, baseInst>;
+ defm "" : SIMDBinary<F64x2, node, name, !add(baseInst, 12)>;
}
// Addition: add
@@ -1139,27 +1089,27 @@ defm PMAX : SIMDBinaryFP<int_wasm_pmax, "pmax", 235>;
// Conversions
//===----------------------------------------------------------------------===//
-multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
- string name, bits<32> simdop> {
- defm op#_#vec_t#_#arg_t :
+multiclass SIMDConvert<Vec vec, Vec arg, SDNode op, string name,
+ bits<32> simdop> {
+ defm op#_#vec :
SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
- [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
- name#"\t$dst, $vec", name, simdop>;
+ [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
+ vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
}
// Floating point to integer with saturation: trunc_sat
-defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 248>;
-defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 249>;
+defm "" : SIMDConvert<I32x4, F32x4, fp_to_sint, "trunc_sat_f32x4_s", 248>;
+defm "" : SIMDConvert<I32x4, F32x4, fp_to_uint, "trunc_sat_f32x4_u", 249>;
// Integer to floating point: convert
-defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 250>;
-defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 251>;
+defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>;
+defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>;
// Lower llvm.wasm.trunc.saturate.* to saturating instructions
def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
- (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
+ (fp_to_sint_I32x4 $src)>;
def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
- (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>;
+ (fp_to_uint_I32x4 $src)>;
// Widening operations
def widen_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
@@ -1168,49 +1118,47 @@ def widen_high_s : SDNode<"WebAssemblyISD::WIDEN_HIGH_S", widen_t>;
def widen_low_u : SDNode<"WebAssemblyISD::WIDEN_LOW_U", widen_t>;
def widen_high_u : SDNode<"WebAssemblyISD::WIDEN_HIGH_U", widen_t>;
-multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
- bits<32> baseInst> {
- defm "" : SIMDConvert<vec_t, arg_t, widen_low_s,
- vec#".widen_low_"#arg#"_s", baseInst>;
- defm "" : SIMDConvert<vec_t, arg_t, widen_high_s,
- vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>;
- defm "" : SIMDConvert<vec_t, arg_t, widen_low_u,
- vec#".widen_low_"#arg#"_u", !add(baseInst, 2)>;
- defm "" : SIMDConvert<vec_t, arg_t, widen_high_u,
- vec#".widen_high_"#arg#"_u", !add(baseInst, 3)>;
+// TODO: refactor this to be uniform for i64x2 if the numbering is not changed.
+multiclass SIMDWiden<Vec vec, bits<32> baseInst> {
+ defm "" : SIMDConvert<vec, vec.split, widen_low_s,
+ "widen_low_"#vec.split.prefix#"_s", baseInst>;
+ defm "" : SIMDConvert<vec, vec.split, widen_high_s,
+ "widen_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>;
+ defm "" : SIMDConvert<vec, vec.split, widen_low_u,
+ "widen_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>;
+ defm "" : SIMDConvert<vec, vec.split, widen_high_u,
+ "widen_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>;
}
-defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 135>;
-defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 167>;
+defm "" : SIMDWiden<I16x8, 135>;
+defm "" : SIMDWiden<I32x4, 167>;
-defm "" : SIMDConvert<v2i64, v4i32, int_wasm_widen_low_signed,
- "i64x2.widen_low_i32x4_s", 199>;
-defm "" : SIMDConvert<v2i64, v4i32, int_wasm_widen_high_signed,
- "i64x2.widen_high_i32x4_s", 200>;
-defm "" : SIMDConvert<v2i64, v4i32, int_wasm_widen_low_unsigned,
- "i64x2.widen_low_i32x4_u", 201>;
-defm "" : SIMDConvert<v2i64, v4i32, int_wasm_widen_high_unsigned,
- "i64x2.widen_high_i32x4_u", 202>;
+defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_low_signed,
+ "widen_low_i32x4_s", 199>;
+defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_high_signed,
+ "widen_high_i32x4_s", 200>;
+defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_low_unsigned,
+ "widen_low_i32x4_u", 201>;
+defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_high_unsigned,
+ "widen_high_i32x4_u", 202>;
// Narrowing operations
-multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg,
- bits<32> baseInst> {
- defm NARROW_S_#vec_t :
+multiclass SIMDNarrow<Vec vec, bits<32> baseInst> {
+ defvar name = vec.split.prefix#".narrow_"#vec.prefix;
+ defm NARROW_S_#vec.split :
SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
- [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed
- (arg_t V128:$low), (arg_t V128:$high))))],
- vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s",
- baseInst>;
- defm NARROW_U_#vec_t :
+ [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed
+ (vec.vt V128:$low), (vec.vt V128:$high))))],
+ name#"_s\t$dst, $low, $high", name#"_s", baseInst>;
+ defm NARROW_U_#vec.split :
SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
- [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned
- (arg_t V128:$low), (arg_t V128:$high))))],
- vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u",
- !add(baseInst, 1)>;
+ [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned
+ (vec.vt V128:$low), (vec.vt V128:$high))))],
+ name#"_u\t$dst, $low, $high", name#"_u", !add(baseInst, 1)>;
}
-defm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 101>;
-defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 133>;
+defm "" : SIMDNarrow<I16x8, 101>;
+defm "" : SIMDNarrow<I32x4, 133>;
// Use narrowing operations for truncating stores. Since the narrowing
// operations are saturating instead of truncating, we need to mask
@@ -1218,89 +1166,74 @@ defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 133>;
// TODO: Use consts instead of splats
def store_v8i8_trunc_v8i16 :
OutPatFrag<(ops node:$val),
- (EXTRACT_LANE_v2i64
- (NARROW_U_v16i8
- (AND_v4i32 (SPLAT_v4i32 (CONST_I32 0x00ff00ff)), node:$val),
- node:$val // Unused input
- ),
- 0
- )>;
+ (EXTRACT_LANE_I64x2
+ (NARROW_U_I8x16
+ (AND (SPLAT_I32x4 (CONST_I32 0x00ff00ff)), node:$val),
+ $val), // Unused input
+ 0)>;
def store_v4i16_trunc_v4i32 :
OutPatFrag<(ops node:$val),
- (EXTRACT_LANE_v2i64
- (NARROW_U_v8i16
- (AND_v4i32 (SPLAT_v4i32 (CONST_I32 0x0000ffff)), node:$val),
- node:$val // Unused input
- ),
- 0
- )>;
+ (EXTRACT_LANE_I64x2
+ (NARROW_U_I16x8
+ (AND (SPLAT_I32x4 (CONST_I32 0x0000ffff)), node:$val),
+ $val), // Unused input
+ 0)>;
// Store patterns adapted from WebAssemblyInstrMemory.td
-multiclass NarrowingStorePatNoOffset<ValueType ty, PatFrag node,
- OutPatFrag out> {
- def : Pat<(node ty:$val, I32:$addr),
- (STORE_I64_A32 0, 0, I32:$addr, (i64 (out ty:$val)))>,
+multiclass NarrowingStorePatNoOffset<Vec vec, OutPatFrag out> {
+ defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits);
+ def : Pat<(node vec.vt:$val, I32:$addr),
+ (STORE_I64_A32 0, 0, $addr, (out $val))>,
Requires<[HasAddr32]>;
- def : Pat<(node ty:$val, I64:$addr),
- (STORE_I64_A64 0, 0, I64:$addr, (i64 (out ty:$val)))>,
+ def : Pat<(node vec.vt:$val, I64:$addr),
+ (STORE_I64_A64 0, 0, $addr, (out $val))>,
Requires<[HasAddr64]>;
}
-defm : NarrowingStorePatNoOffset<v8i16, truncstorevi8, store_v8i8_trunc_v8i16>;
-defm : NarrowingStorePatNoOffset<v4i32, truncstorevi16,
- store_v4i16_trunc_v4i32>;
+defm : NarrowingStorePatNoOffset<I16x8, store_v8i8_trunc_v8i16>;
+defm : NarrowingStorePatNoOffset<I32x4, store_v4i16_trunc_v4i32>;
-multiclass NarrowingStorePatImmOff<ValueType ty, PatFrag kind,
- PatFrag operand, OutPatFrag out> {
- def : Pat<(kind ty:$val, (operand I32:$addr, imm:$off)),
- (STORE_I64_A32 0, imm:$off, I32:$addr, (i64 (out ty:$val)))>,
+multiclass NarrowingStorePatImmOff<Vec vec, PatFrag operand, OutPatFrag out> {
+ defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits);
+ def : Pat<(node vec.vt:$val, (operand I32:$addr, imm:$off)),
+ (STORE_I64_A32 0, imm:$off, $addr, (out $val))>,
Requires<[HasAddr32]>;
- def : Pat<(kind ty:$val, (operand I64:$addr, imm:$off)),
- (STORE_I64_A64 0, imm:$off, I64:$addr, (i64 (out ty:$val)))>,
+ def : Pat<(node vec.vt:$val, (operand I64:$addr, imm:$off)),
+ (STORE_I64_A64 0, imm:$off, $addr, (out $val))>,
Requires<[HasAddr64]>;
}
-defm : NarrowingStorePatImmOff<v8i16, truncstorevi8, regPlusImm,
- store_v8i8_trunc_v8i16>;
-defm : NarrowingStorePatImmOff<v4i32, truncstorevi16, regPlusImm,
- store_v4i16_trunc_v4i32>;
-defm : NarrowingStorePatImmOff<v8i16, truncstorevi8, or_is_add,
- store_v8i8_trunc_v8i16>;
-defm : NarrowingStorePatImmOff<v4i32, truncstorevi16, or_is_add,
- store_v4i16_trunc_v4i32>;
-
-multiclass NarrowingStorePatOffsetOnly<ValueType ty, PatFrag kind,
- OutPatFrag out> {
- def : Pat<(kind ty:$val, imm:$off),
- (STORE_I64_A32 0, imm:$off, (CONST_I32 0), (i64 (out ty:$val)))>,
+defm : NarrowingStorePatImmOff<I16x8, regPlusImm, store_v8i8_trunc_v8i16>;
+defm : NarrowingStorePatImmOff<I32x4, regPlusImm, store_v4i16_trunc_v4i32>;
+defm : NarrowingStorePatImmOff<I16x8, or_is_add, store_v8i8_trunc_v8i16>;
+defm : NarrowingStorePatImmOff<I32x4, or_is_add, store_v4i16_trunc_v4i32>;
+
+multiclass NarrowingStorePatOffsetOnly<Vec vec, OutPatFrag out> {
+ defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits);
+ def : Pat<(node vec.vt:$val, imm:$off),
+ (STORE_I64_A32 0, imm:$off, (CONST_I32 0), (out $val))>,
Requires<[HasAddr32]>;
- def : Pat<(kind ty:$val, imm:$off),
- (STORE_I64_A64 0, imm:$off, (CONST_I64 0), (i64 (out ty:$val)))>,
+ def : Pat<(node vec.vt:$val, imm:$off),
+ (STORE_I64_A64 0, imm:$off, (CONST_I64 0), (out $val))>,
Requires<[HasAddr64]>;
}
-defm : NarrowingStorePatOffsetOnly<v8i16, truncstorevi8,
- store_v8i8_trunc_v8i16>;
-defm : NarrowingStorePatOffsetOnly<v4i32, truncstorevi16,
- store_v4i16_trunc_v4i32>;
+defm : NarrowingStorePatOffsetOnly<I16x8, store_v8i8_trunc_v8i16>;
+defm : NarrowingStorePatOffsetOnly<I32x4, store_v4i16_trunc_v4i32>;
-multiclass NarrowingStorePatGlobalAddrOffOnly<ValueType ty, PatFrag kind,
- OutPatFrag out> {
- def : Pat<(kind ty:$val, (WebAssemblywrapper tglobaladdr:$off)),
- (STORE_I64_A32
- 0, tglobaladdr:$off, (CONST_I32 0), (i64 (out ty:$val)))>,
+multiclass NarrowingStorePatGlobalAddrOffOnly<Vec vec, OutPatFrag out> {
+ defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits);
+ def : Pat<(node vec.vt:$val, (WebAssemblywrapper tglobaladdr:$off)),
+ (STORE_I64_A32 0, tglobaladdr:$off, (CONST_I32 0), (out $val))>,
Requires<[IsNotPIC, HasAddr32]>;
- def : Pat<(kind ty:$val, (WebAssemblywrapper tglobaladdr:$off)),
- (STORE_I64_A64
- 0, tglobaladdr:$off, (CONST_I64 0), (i64 (out ty:$val)))>,
+ def : Pat<(node vec.vt:$val, (WebAssemblywrapper tglobaladdr:$off)),
+ (STORE_I64_A64 0, tglobaladdr:$off, (CONST_I64 0), (out $val))>,
Requires<[IsNotPIC, HasAddr64]>;
}
-defm : NarrowingStorePatGlobalAddrOffOnly<v8i16, truncstorevi8,
- store_v8i8_trunc_v8i16>;
-defm : NarrowingStorePatGlobalAddrOffOnly<v4i32, truncstorevi16,
- store_v4i16_trunc_v4i32>;
+defm : NarrowingStorePatGlobalAddrOffOnly<I16x8, store_v8i8_trunc_v8i16>;
+defm : NarrowingStorePatGlobalAddrOffOnly<I32x4, store_v4i16_trunc_v4i32>;
// Bitcasts are nops
// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
@@ -1317,29 +1250,27 @@ def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS)
//===----------------------------------------------------------------------===//
-multiclass SIMDQFM<ValueType vec_t, string vec, bits<32> simdopA,
- bits<32> simdopS> {
- defm QFMA_#vec_t :
+multiclass SIMDQFM<Vec vec, bits<32> simdopA, bits<32> simdopS> {
+ defm QFMA_#vec :
SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),
(outs), (ins),
- [(set (vec_t V128:$dst),
- (int_wasm_qfma (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))],
- vec#".qfma\t$dst, $a, $b, $c", vec#".qfma", simdopA>;
- defm QFMS_#vec_t :
+ [(set (vec.vt V128:$dst), (int_wasm_qfma
+ (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
+ vec.prefix#".qfma\t$dst, $a, $b, $c", vec.prefix#".qfma", simdopA>;
+ defm QFMS_#vec :
SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),
(outs), (ins),
- [(set (vec_t V128:$dst),
- (int_wasm_qfms (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))],
- vec#".qfms\t$dst, $a, $b, $c", vec#".qfms", simdopS>;
+ [(set (vec.vt V128:$dst), (int_wasm_qfms
+ (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
+ vec.prefix#".qfms\t$dst, $a, $b, $c", vec.prefix#".qfms", simdopS>;
}
-defm "" : SIMDQFM<v4f32, "f32x4", 180, 212>;
-defm "" : SIMDQFM<v2f64, "f64x2", 254, 255>;
+defm "" : SIMDQFM<F32x4, 180, 212>;
+defm "" : SIMDQFM<F64x2, 254, 255>;
//===----------------------------------------------------------------------===//
// Saturating Rounding Q-Format Multiplication
//===----------------------------------------------------------------------===//
defm Q15MULR_SAT_S :
- SIMDBinary<v8i16, "i16x8", int_wasm_q15mulr_saturate_signed, "q15mulr_sat_s",
- 156>;
+ SIMDBinary<I16x8, int_wasm_q15mulr_saturate_signed, "q15mulr_sat_s", 156>;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
index e866059cf0ab..3943148f138e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
@@ -123,7 +123,7 @@ static void convertImplicitDefToConstZero(MachineInstr *MI,
} else if (RegClass == &WebAssembly::V128RegClass) {
// TODO: Replace this with v128.const 0 once that is supported in V8
Register TempReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
- MI->setDesc(TII->get(WebAssembly::SPLAT_v4i32));
+ MI->setDesc(TII->get(WebAssembly::SPLAT_I32x4));
MI->addOperand(MachineOperand::CreateReg(TempReg, false));
MachineInstr *Const = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII->get(WebAssembly::CONST_I32), TempReg)
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