[llvm-branch-commits] [llvm] cf8f682 - [RISCV] Adjust tested vor ops for more stable tests. NFC.
Fraser Cormack via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Dec 28 11:44:11 PST 2020
Author: Fraser Cormack
Date: 2020-12-28T19:33:25Z
New Revision: cf8f682c2dd478d76e729f5d998e56b9acef8aa4
URL: https://github.com/llvm/llvm-project/commit/cf8f682c2dd478d76e729f5d998e56b9acef8aa4
DIFF: https://github.com/llvm/llvm-project/commit/cf8f682c2dd478d76e729f5d998e56b9acef8aa4.diff
LOG: [RISCV] Adjust tested vor ops for more stable tests. NFC.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
index f07f7fdea176..410da16bc3ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
@@ -17,9 +17,9 @@ define <vscale x 1 x i8> @vor_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 1 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = or <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
@@ -66,9 +66,9 @@ define <vscale x 2 x i8> @vor_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 2 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = or <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
@@ -115,9 +115,9 @@ define <vscale x 4 x i8> @vor_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 4 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = or <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
@@ -164,9 +164,9 @@ define <vscale x 8 x i8> @vor_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 8 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
@@ -213,9 +213,9 @@ define <vscale x 16 x i8> @vor_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 16 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = or <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
@@ -262,9 +262,9 @@ define <vscale x 32 x i8> @vor_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 32 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = or <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
@@ -311,9 +311,9 @@ define <vscale x 64 x i8> @vor_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 64 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = or <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
@@ -360,9 +360,9 @@ define <vscale x 1 x i16> @vor_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 1 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = or <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
@@ -409,9 +409,9 @@ define <vscale x 2 x i16> @vor_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 2 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = or <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
@@ -458,9 +458,9 @@ define <vscale x 4 x i16> @vor_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 4 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = or <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
@@ -507,9 +507,9 @@ define <vscale x 8 x i16> @vor_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 8 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
@@ -556,9 +556,9 @@ define <vscale x 16 x i16> @vor_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 16 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = or <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
@@ -605,9 +605,9 @@ define <vscale x 32 x i16> @vor_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 32 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = or <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
@@ -654,9 +654,9 @@ define <vscale x 1 x i32> @vor_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 1 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = or <vscale x 1 x i32> %va, %splat
ret <vscale x 1 x i32> %vc
@@ -703,9 +703,9 @@ define <vscale x 2 x i32> @vor_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 2 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = or <vscale x 2 x i32> %va, %splat
ret <vscale x 2 x i32> %vc
@@ -752,9 +752,9 @@ define <vscale x 4 x i32> @vor_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 4 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = or <vscale x 4 x i32> %va, %splat
ret <vscale x 4 x i32> %vc
@@ -801,9 +801,9 @@ define <vscale x 8 x i32> @vor_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 8 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i32> %vc
@@ -850,9 +850,9 @@ define <vscale x 16 x i32> @vor_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 16 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%vc = or <vscale x 16 x i32> %va, %splat
ret <vscale x 16 x i32> %vc
@@ -906,9 +906,9 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vor_vx_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
+ %head = insertelement <vscale x 1 x i64> undef, i64 -12, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%vc = or <vscale x 1 x i64> %va, %splat
ret <vscale x 1 x i64> %vc
@@ -962,9 +962,9 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vor_vx_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
+ %head = insertelement <vscale x 2 x i64> undef, i64 -12, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%vc = or <vscale x 2 x i64> %va, %splat
ret <vscale x 2 x i64> %vc
@@ -1018,9 +1018,9 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vor_vx_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
+ %head = insertelement <vscale x 4 x i64> undef, i64 -12, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%vc = or <vscale x 4 x i64> %va, %splat
ret <vscale x 4 x i64> %vc
@@ -1074,9 +1074,9 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vor_vx_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
+ %head = insertelement <vscale x 8 x i64> undef, i64 -12, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
index 7de487cb0a76..04aa0de912a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
@@ -17,9 +17,9 @@ define <vscale x 1 x i8> @vor_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 1 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = or <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
@@ -66,9 +66,9 @@ define <vscale x 2 x i8> @vor_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 2 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = or <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
@@ -115,9 +115,9 @@ define <vscale x 4 x i8> @vor_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 4 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = or <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
@@ -164,9 +164,9 @@ define <vscale x 8 x i8> @vor_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 8 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
@@ -213,9 +213,9 @@ define <vscale x 16 x i8> @vor_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 16 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = or <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
@@ -262,9 +262,9 @@ define <vscale x 32 x i8> @vor_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 32 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = or <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
@@ -311,9 +311,9 @@ define <vscale x 64 x i8> @vor_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vor_vx_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
+ %head = insertelement <vscale x 64 x i8> undef, i8 -12, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = or <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
@@ -360,9 +360,9 @@ define <vscale x 1 x i16> @vor_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 1 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = or <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
@@ -409,9 +409,9 @@ define <vscale x 2 x i16> @vor_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 2 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = or <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
@@ -458,9 +458,9 @@ define <vscale x 4 x i16> @vor_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 4 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = or <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
@@ -507,9 +507,9 @@ define <vscale x 8 x i16> @vor_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 8 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
@@ -556,9 +556,9 @@ define <vscale x 16 x i16> @vor_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 16 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = or <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
@@ -605,9 +605,9 @@ define <vscale x 32 x i16> @vor_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vor_vx_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
+ %head = insertelement <vscale x 32 x i16> undef, i16 -12, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = or <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
@@ -654,9 +654,9 @@ define <vscale x 1 x i32> @vor_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 1 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = or <vscale x 1 x i32> %va, %splat
ret <vscale x 1 x i32> %vc
@@ -703,9 +703,9 @@ define <vscale x 2 x i32> @vor_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 2 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = or <vscale x 2 x i32> %va, %splat
ret <vscale x 2 x i32> %vc
@@ -752,9 +752,9 @@ define <vscale x 4 x i32> @vor_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 4 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = or <vscale x 4 x i32> %va, %splat
ret <vscale x 4 x i32> %vc
@@ -801,9 +801,9 @@ define <vscale x 8 x i32> @vor_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 8 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i32> %vc
@@ -850,9 +850,9 @@ define <vscale x 16 x i32> @vor_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vor_vx_nxv16i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
+ %head = insertelement <vscale x 16 x i32> undef, i32 -12, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%vc = or <vscale x 16 x i32> %va, %splat
ret <vscale x 16 x i32> %vc
@@ -899,9 +899,9 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vor_vx_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
+ %head = insertelement <vscale x 1 x i64> undef, i64 -12, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%vc = or <vscale x 1 x i64> %va, %splat
ret <vscale x 1 x i64> %vc
@@ -948,9 +948,9 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vor_vx_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
+ %head = insertelement <vscale x 2 x i64> undef, i64 -12, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%vc = or <vscale x 2 x i64> %va, %splat
ret <vscale x 2 x i64> %vc
@@ -997,9 +997,9 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vor_vx_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
+ %head = insertelement <vscale x 4 x i64> undef, i64 -12, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%vc = or <vscale x 4 x i64> %va, %splat
ret <vscale x 4 x i64> %vc
@@ -1046,9 +1046,9 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vor_vx_nxv8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT: vor.vi v16, v16, -1
+; CHECK-NEXT: vor.vi v16, v16, -12
; CHECK-NEXT: ret
- %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
+ %head = insertelement <vscale x 8 x i64> undef, i64 -12, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc
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