[llvm-branch-commits] [llvm] d6ff5cf - [Target] Use llvm::any_of (NFC)
Kazu Hirata via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Dec 24 19:47:56 PST 2020
Author: Kazu Hirata
Date: 2020-12-24T19:43:26-08:00
New Revision: d6ff5cf995db22c37890b5469a5ad62022996c8c
URL: https://github.com/llvm/llvm-project/commit/d6ff5cf995db22c37890b5469a5ad62022996c8c
DIFF: https://github.com/llvm/llvm-project/commit/d6ff5cf995db22c37890b5469a5ad62022996c8c.diff
LOG: [Target] Use llvm::any_of (NFC)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/tools/llvm-lipo/llvm-lipo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 86cfdf8f7cf9..954b0960fc02 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -333,9 +333,9 @@ bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
}
bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
- return std::any_of(std::begin(*AArch64::GPR64argRegClass.MC),
- std::end(*AArch64::GPR64argRegClass.MC),
- [this, &MF](MCPhysReg r){return isReservedReg(MF, r);});
+ return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
+ return isReservedReg(MF, r);
+ });
}
void AArch64RegisterInfo::emitReservedArgRegCallError(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
index edc5fe287167..85d26cd4d0ff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
@@ -325,9 +325,10 @@ bool AMDGPURewriteOutArguments::runOnFunction(Function &F) {
Value *ReplVal = Store.second->getValueOperand();
auto &ValVec = Replacements[Store.first];
- if (llvm::find_if(ValVec,
- [OutArg](const std::pair<Argument *, Value *> &Entry) {
- return Entry.first == OutArg;}) != ValVec.end()) {
+ if (llvm::any_of(ValVec,
+ [OutArg](const std::pair<Argument *, Value *> &Entry) {
+ return Entry.first == OutArg;
+ })) {
LLVM_DEBUG(dbgs()
<< "Saw multiple out arg stores" << *OutArg << '\n');
// It is possible to see stores to the same argument multiple times,
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 06cce54e540c..d86527df5c3c 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -560,8 +560,9 @@ static bool tryToFoldACImm(const SIInstrInfo *TII,
if (!UseReg.isVirtual())
return false;
- if (llvm::find_if(FoldList, [UseMI](const FoldCandidate &FC) {
- return FC.UseMI == UseMI; }) != FoldList.end())
+ if (llvm::any_of(FoldList, [UseMI](const FoldCandidate &FC) {
+ return FC.UseMI == UseMI;
+ }))
return false;
MachineRegisterInfo &MRI = UseMI->getParent()->getParent()->getRegInfo();
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c0037fb623ee..92bb316356c6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3434,7 +3434,7 @@ void RISCVTargetLowering::validateCCReservedRegs(
const Function &F = MF.getFunction();
const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
- if (std::any_of(std::begin(Regs), std::end(Regs), [&STI](auto Reg) {
+ if (llvm::any_of(Regs, [&STI](auto Reg) {
return STI.isRegisterReservedByUser(Reg.first);
}))
F.getContext().diagnose(DiagnosticInfoUnsupported{
diff --git a/llvm/tools/llvm-lipo/llvm-lipo.cpp b/llvm/tools/llvm-lipo/llvm-lipo.cpp
index 6761f9951e58..7fbe489ecc6f 100644
--- a/llvm/tools/llvm-lipo/llvm-lipo.cpp
+++ b/llvm/tools/llvm-lipo/llvm-lipo.cpp
@@ -538,9 +538,8 @@ static void updateAlignments(Range &Slices,
static void checkUnusedAlignments(ArrayRef<Slice> Slices,
const StringMap<const uint32_t> &Alignments) {
auto HasArch = [&](StringRef Arch) {
- return llvm::find_if(Slices, [Arch](Slice S) {
- return S.getArchString() == Arch;
- }) != Slices.end();
+ return llvm::any_of(Slices,
+ [Arch](Slice S) { return S.getArchString() == Arch; });
};
for (StringRef Arch : Alignments.keys())
if (!HasArch(Arch))
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