[llvm-branch-commits] [llvm] 8bf9cde - AMDGPU: Use Register

[Matt Arsenault via llvm-branch-commits]

Author: Matt Arsenault
Date: 2020-12-22T21:55:59-05:00
New Revision: 8bf9cdeaee4834bcba35322f1d84c57c691d2244

URL: https://github.com/llvm/llvm-project/commit/8bf9cdeaee4834bcba35322f1d84c57c691d2244
DIFF: https://github.com/llvm/llvm-project/commit/8bf9cdeaee4834bcba35322f1d84c57c691d2244.diff

LOG: AMDGPU: Use Register

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 65c7f49b646c..939a9676ad3b 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -98,7 +98,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
   if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
     for (const CalleeSavedInfo &CS : CSI) {
       // Insert the spill to the stack frame.
-      unsigned Reg = CS.getReg();
+      MCRegister Reg = CS.getReg();
 
       MachineInstrSpan MIS(I, &SaveBlock);
       const TargetRegisterClass *RC =
@@ -217,7 +217,8 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
     const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
 
     for (unsigned I = 0; CSRegs[I]; ++I) {
-      unsigned Reg = CSRegs[I];
+      MCRegister Reg = CSRegs[I];
+
       if (SavedRegs.test(Reg)) {
         const TargetRegisterClass *RC =
           TRI->getMinimalPhysRegClass(Reg, MVT::i32);