[llvm-branch-commits] [llvm] a781a70 - [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats
Thomas Lively via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Dec 22 14:33:40 PST 2020
Author: Thomas Lively
Date: 2020-12-22T14:29:06-08:00
New Revision: a781a706b961a348006b604cdff8b555e62a2fcb
URL: https://github.com/llvm/llvm-project/commit/a781a706b961a348006b604cdff8b555e62a2fcb
DIFF: https://github.com/llvm/llvm-project/commit/a781a706b961a348006b604cdff8b555e62a2fcb.diff
LOG: [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats
These instructions previously used prefixes like v8x16 to signify that they were
agnostic between float and int interpretations. We renamed these instructions to
remove this form of prefix in https://github.com/WebAssembly/simd/issues/297 and
https://github.com/WebAssembly/simd/issues/316 and this commit brings the names
in LLVM up to date.
Differential Revision: https://reviews.llvm.org/D93722
Added:
Modified:
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
llvm/test/CodeGen/WebAssembly/simd-offset.ll
llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
llvm/test/CodeGen/WebAssembly/simd.ll
llvm/test/MC/Disassembler/WebAssembly/wasm.txt
llvm/test/MC/WebAssembly/simd-encodings.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
index fccee4b96ed5..4bc77aa68668 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
@@ -194,7 +194,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64)
WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
- WASM_LOAD_STORE(LOAD_SPLAT_v8x16)
+ WASM_LOAD_STORE(LOAD8_SPLAT)
WASM_LOAD_STORE(LOAD_LANE_v16i8)
WASM_LOAD_STORE(STORE_LANE_v16i8)
return 0;
@@ -222,7 +222,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64)
WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
- WASM_LOAD_STORE(LOAD_SPLAT_v16x8)
+ WASM_LOAD_STORE(LOAD16_SPLAT)
WASM_LOAD_STORE(LOAD_LANE_v8i16)
WASM_LOAD_STORE(STORE_LANE_v8i16)
return 1;
@@ -253,7 +253,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64)
WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
- WASM_LOAD_STORE(LOAD_SPLAT_v32x4)
+ WASM_LOAD_STORE(LOAD32_SPLAT)
WASM_LOAD_STORE(LOAD_ZERO_v4i32)
WASM_LOAD_STORE(LOAD_LANE_v4i32)
WASM_LOAD_STORE(STORE_LANE_v4i32)
@@ -272,7 +272,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64)
WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
- WASM_LOAD_STORE(LOAD_SPLAT_v64x2)
+ WASM_LOAD_STORE(LOAD64_SPLAT)
WASM_LOAD_STORE(LOAD_EXTEND_S_v8i16)
WASM_LOAD_STORE(LOAD_EXTEND_U_v8i16)
WASM_LOAD_STORE(LOAD_EXTEND_S_v4i32)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 191cdea0c0ae..e48bbaebd47e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -64,55 +64,55 @@ defm : LoadPatOffsetOnly<vec_t, load, "LOAD_V128">;
defm : LoadPatGlobalAddrOffOnly<vec_t, load, "LOAD_V128">;
}
-// vNxM.load_splat
-multiclass SIMDLoadSplat<string vec, bits<32> simdop> {
+// v128.loadX_splat
+multiclass SIMDLoadSplat<int size, bits<32> simdop> {
let mayLoad = 1, UseNamedOperandTable = 1 in {
- defm LOAD_SPLAT_#vec#_A32 :
+ defm LOAD#size#_SPLAT_A32 :
SIMD_I<(outs V128:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
(outs),
(ins P2Align:$p2align, offset32_op:$off), [],
- vec#".load_splat\t$dst, ${off}(${addr})$p2align",
- vec#".load_splat\t$off$p2align", simdop>;
- defm LOAD_SPLAT_#vec#_A64 :
+ "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
+ "v128.load"#size#"_splat\t$off$p2align", simdop>;
+ defm LOAD#size#_SPLAT_A64 :
SIMD_I<(outs V128:$dst),
(ins P2Align:$p2align, offset64_op:$off, I64:$addr),
(outs),
(ins P2Align:$p2align, offset64_op:$off), [],
- vec#".load_splat\t$dst, ${off}(${addr})$p2align",
- vec#".load_splat\t$off$p2align", simdop>;
+ "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
+ "v128.load"#size#"_splat\t$off$p2align", simdop>;
}
}
-defm "" : SIMDLoadSplat<"v8x16", 7>;
-defm "" : SIMDLoadSplat<"v16x8", 8>;
-defm "" : SIMDLoadSplat<"v32x4", 9>;
-defm "" : SIMDLoadSplat<"v64x2", 10>;
+defm "" : SIMDLoadSplat<8, 7>;
+defm "" : SIMDLoadSplat<16, 8>;
+defm "" : SIMDLoadSplat<32, 9>;
+defm "" : SIMDLoadSplat<64, 10>;
def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>;
def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>;
-foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"],
- ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in {
+foreach args = [["v16i8", "8"], ["v8i16", "16"], ["v4i32", "32"],
+ ["v2i64", "64"], ["v4f32", "32"], ["v2f64", "64"]] in {
defm : LoadPatNoOffset<!cast<ValueType>(args[0]),
load_splat,
- "LOAD_SPLAT_"#args[1]>;
+ "LOAD"#args[1]#"_SPLAT">;
defm : LoadPatImmOff<!cast<ValueType>(args[0]),
load_splat,
regPlusImm,
- "LOAD_SPLAT_"#args[1]>;
+ "LOAD"#args[1]#"_SPLAT">;
defm : LoadPatImmOff<!cast<ValueType>(args[0]),
load_splat,
or_is_add,
- "LOAD_SPLAT_"#args[1]>;
+ "LOAD"#args[1]#"_SPLAT">;
defm : LoadPatOffsetOnly<!cast<ValueType>(args[0]),
load_splat,
- "LOAD_SPLAT_"#args[1]>;
+ "LOAD"#args[1]#"_SPLAT">;
defm : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
load_splat,
- "LOAD_SPLAT_"#args[1]>;
+ "LOAD"#args[1]#"_SPLAT">;
}
// Load and extend
@@ -401,10 +401,10 @@ defm SHUFFLE :
vec_i8imm_op:$mC, vec_i8imm_op:$mD,
vec_i8imm_op:$mE, vec_i8imm_op:$mF),
[],
- "v8x16.shuffle\t$dst, $x, $y, "#
+ "i8x16.shuffle\t$dst, $x, $y, "#
"$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
"$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
- "v8x16.shuffle\t"#
+ "i8x16.shuffle\t"#
"$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
"$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
13>;
@@ -433,14 +433,14 @@ def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
(i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
}
-// Swizzle lanes: v8x16.swizzle
+// Swizzle lanes: i8x16.swizzle
def wasm_swizzle_t : SDTypeProfile<1, 2, []>;
def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>;
defm SWIZZLE :
SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
[(set (v16i8 V128:$dst),
(wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
- "v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 14>;
+ "i8x16.swizzle\t$dst, $src, $mask", "i8x16.swizzle", 14>;
def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
(SWIZZLE V128:$src, V128:$mask)>;
diff --git a/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll b/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
index 4f7588787378..1360e0172d3f 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
@@ -178,7 +178,7 @@ define <8 x i16> @splat_common_arg_i16x8(i16 %a, i16 %b, i16 %c) {
; CHECK-LABEL: swizzle_one_i8x16:
; CHECK-NEXT: .functype swizzle_one_i8x16 (v128, v128) -> (v128)
-; CHECK-NEXT: v8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
+; CHECK-NEXT: i8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
; CHECK-NEXT: return $pop[[L0]]
define <16 x i8> @swizzle_one_i8x16(<16 x i8> %src, <16 x i8> %mask) {
%m0 = extractelement <16 x i8> %mask, i32 0
@@ -189,7 +189,7 @@ define <16 x i8> @swizzle_one_i8x16(<16 x i8> %src, <16 x i8> %mask) {
; CHECK-LABEL: swizzle_all_i8x16:
; CHECK-NEXT: .functype swizzle_all_i8x16 (v128, v128) -> (v128)
-; CHECK-NEXT: v8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
+; CHECK-NEXT: i8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
; CHECK-NEXT: return $pop[[L0]]
define <16 x i8> @swizzle_all_i8x16(<16 x i8> %src, <16 x i8> %mask) {
%m0 = extractelement <16 x i8> %mask, i32 0
@@ -256,7 +256,7 @@ define <8 x i16> @swizzle_one_i16x8(<8 x i16> %src, <8 x i16> %mask) {
; CHECK-LABEL: mashup_swizzle_i8x16:
; CHECK-NEXT: .functype mashup_swizzle_i8x16 (v128, v128, i32) -> (v128)
-; CHECK-NEXT: v8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
+; CHECK-NEXT: i8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
; CHECK: i8x16.replace_lane
; CHECK: i8x16.replace_lane
; CHECK: i8x16.replace_lane
diff --git a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
index 23a7bfbde927..da7343770de7 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -13,7 +13,7 @@ target triple = "wasm32-unknown-unknown"
; ==============================================================================
; CHECK-LABEL: swizzle_v16i8:
; SIMD128-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>)
define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
@@ -164,9 +164,9 @@ define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
}
; CHECK-LABEL: shuffle_v16i8:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <16 x i8> @llvm.wasm.shuffle(
@@ -180,9 +180,9 @@ define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
}
; CHECK-LABEL: shuffle_undef_v16i8:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
diff --git a/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll b/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
index 4e693c285a3f..3d08a586edb5 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
@@ -9,7 +9,7 @@ target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: load_splat:
; CHECK-NEXT: .functype load_splat (i32, i32) -> (i32)
; CHECK-NEXT: i32.load8_u $[[E:[0-9]+]]=, 0($0){{$}}
-; CHECK-NEXT: v8x16.load_splat $push[[V:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load8_splat $push[[V:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: v128.store 0($1), $pop[[V]]{{$}}
; CHECK-NEXT: return $[[E]]{{$}}
define i8 @load_splat(i8* %p, <16 x i8>* %out) {
diff --git a/llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll b/llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
index 8ebeb15ccc9a..000b7730e3bf 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
@@ -89,11 +89,11 @@ define void @store_v16i8_a32(<16 x i8> *%p, <16 x i8> %v) {
ret void
}
-; 1 is the default alignment for v8x16.load_splat so no attribute is needed.
+; 1 is the default alignment for v128.load8_splat so no attribute is needed.
; CHECK-LABEL: load_splat_v16i8_a1:
; CHECK-NEXT: .functype load_splat_v16i8_a1 (i32) -> (v128){{$}}
-; CHECK-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load8_splat $push[[R:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <16 x i8> @load_splat_v16i8_a1(i8* %p) {
%e = load i8, i8* %p, align 1
@@ -106,7 +106,7 @@ define <16 x i8> @load_splat_v16i8_a1(i8* %p) {
; CHECK-LABEL: load_splat_v16i8_a2:
; CHECK-NEXT: .functype load_splat_v16i8_a2 (i32) -> (v128){{$}}
-; CHECK-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load8_splat $push[[R:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <16 x i8> @load_splat_v16i8_a2(i8* %p) {
%e = load i8, i8* %p, align 2
@@ -304,7 +304,7 @@ define <8 x i16> @load_sext_v8i16_a16(<8 x i8>* %p) {
; CHECK-LABEL: load_splat_v8i16_a1:
; CHECK-NEXT: .functype load_splat_v8i16_a1 (i32) -> (v128){{$}}
-; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
+; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @load_splat_v8i16_a1(i16* %p) {
%e = load i16, i16* %p, align 1
@@ -313,11 +313,11 @@ define <8 x i16> @load_splat_v8i16_a1(i16* %p) {
ret <8 x i16> %v2
}
-; 2 is the default alignment for v16x8.load_splat so no attribute is needed.
+; 2 is the default alignment for v128.load16_splat so no attribute is needed.
; CHECK-LABEL: load_splat_v8i16_a2:
; CHECK-NEXT: .functype load_splat_v8i16_a2 (i32) -> (v128){{$}}
-; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @load_splat_v8i16_a2(i16* %p) {
%e = load i16, i16* %p, align 2
@@ -330,7 +330,7 @@ define <8 x i16> @load_splat_v8i16_a2(i16* %p) {
; CHECK-LABEL: load_splat_v8i16_a4:
; CHECK-NEXT: .functype load_splat_v8i16_a4 (i32) -> (v128){{$}}
-; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @load_splat_v8i16_a4(i16* %p) {
%e = load i16, i16* %p, align 4
@@ -528,7 +528,7 @@ define <4 x i32> @load_sext_v4i32_a16(<4 x i16>* %p) {
; CHECK-LABEL: load_splat_v4i32_a1:
; CHECK-NEXT: .functype load_splat_v4i32_a1 (i32) -> (v128){{$}}
-; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
+; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @load_splat_v4i32_a1(i32* %addr) {
%e = load i32, i32* %addr, align 1
@@ -539,7 +539,7 @@ define <4 x i32> @load_splat_v4i32_a1(i32* %addr) {
; CHECK-LABEL: load_splat_v4i32_a2:
; CHECK-NEXT: .functype load_splat_v4i32_a2 (i32) -> (v128){{$}}
-; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
+; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @load_splat_v4i32_a2(i32* %addr) {
%e = load i32, i32* %addr, align 2
@@ -548,11 +548,11 @@ define <4 x i32> @load_splat_v4i32_a2(i32* %addr) {
ret <4 x i32> %v2
}
-; 4 is the default alignment for v32x4.load_splat so no attribute is needed.
+; 4 is the default alignment for v128.load32_splat so no attribute is needed.
; CHECK-LABEL: load_splat_v4i32_a4:
; CHECK-NEXT: .functype load_splat_v4i32_a4 (i32) -> (v128){{$}}
-; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @load_splat_v4i32_a4(i32* %addr) {
%e = load i32, i32* %addr, align 4
@@ -565,7 +565,7 @@ define <4 x i32> @load_splat_v4i32_a4(i32* %addr) {
; CHECK-LABEL: load_splat_v4i32_a8:
; CHECK-NEXT: .functype load_splat_v4i32_a8 (i32) -> (v128){{$}}
-; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @load_splat_v4i32_a8(i32* %addr) {
%e = load i32, i32* %addr, align 8
@@ -660,7 +660,7 @@ define void @store_v2i64_a32(<2 x i64> *%p, <2 x i64> %v) {
; CHECK-LABEL: load_splat_v2i64_a1:
; CHECK-NEXT: .functype load_splat_v2i64_a1 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @load_splat_v2i64_a1(i64* %p) {
%e = load i64, i64* %p, align 1
@@ -671,7 +671,7 @@ define <2 x i64> @load_splat_v2i64_a1(i64* %p) {
; CHECK-LABEL: load_splat_v2i64_a2:
; CHECK-NEXT: .functype load_splat_v2i64_a2 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @load_splat_v2i64_a2(i64* %p) {
%e = load i64, i64* %p, align 2
@@ -682,7 +682,7 @@ define <2 x i64> @load_splat_v2i64_a2(i64* %p) {
; CHECK-LABEL: load_splat_v2i64_a4:
; CHECK-NEXT: .functype load_splat_v2i64_a4 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @load_splat_v2i64_a4(i64* %p) {
%e = load i64, i64* %p, align 4
@@ -691,11 +691,11 @@ define <2 x i64> @load_splat_v2i64_a4(i64* %p) {
ret <2 x i64> %v2
}
-; 8 is the default alignment for v64x2.load_splat so no attribute is needed.
+; 8 is the default alignment for v128.load64_splat so no attribute is needed.
; CHECK-LABEL: load_splat_v2i64_a8:
; CHECK-NEXT: .functype load_splat_v2i64_a8 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @load_splat_v2i64_a8(i64* %p) {
%e = load i64, i64* %p, align 8
@@ -708,7 +708,7 @@ define <2 x i64> @load_splat_v2i64_a8(i64* %p) {
; CHECK-LABEL: load_splat_v2i64_a16:
; CHECK-NEXT: .functype load_splat_v2i64_a16 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @load_splat_v2i64_a16(i64* %p) {
%e = load i64, i64* %p, align 16
diff --git a/llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll b/llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
index 597ab58e879e..b72086a2d6cb 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
@@ -6,7 +6,7 @@
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown"
-; CHECK: v8x16.shuffle
+; CHECK: i8x16.shuffle
define <4 x i32> @foo(<4 x i32> %x) {
%1 = shufflevector <4 x i32> %x, <4 x i32> undef,
<4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
diff --git a/llvm/test/CodeGen/WebAssembly/simd-offset.ll b/llvm/test/CodeGen/WebAssembly/simd-offset.ll
index b2d32936df13..fb41653a514a 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-offset.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-offset.ll
@@ -25,7 +25,7 @@ define <16 x i8> @load_splat_v16i8(i8* %p) {
; CHECK: .functype load_splat_v16i8 (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v8x16.load_splat 0
+; CHECK-NEXT: v128.load8_splat 0
; CHECK-NEXT: # fallthrough-return
%e = load i8, i8* %p
%v1 = insertelement <16 x i8> undef, i8 %e, i32 0
@@ -52,7 +52,7 @@ define <16 x i8> @load_splat_v16i8_with_folded_offset(i8* %p) {
; CHECK: .functype load_splat_v16i8_with_folded_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v8x16.load_splat 16
+; CHECK-NEXT: v128.load8_splat 16
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint i8* %p to i32
%r = add nuw i32 %q, 16
@@ -80,7 +80,7 @@ define <16 x i8> @load_splat_v16i8_with_folded_gep_offset(i8* %p) {
; CHECK: .functype load_splat_v16i8_with_folded_gep_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v8x16.load_splat 1
+; CHECK-NEXT: v128.load8_splat 1
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds i8, i8* %p, i32 1
%e = load i8, i8* %s
@@ -110,7 +110,7 @@ define <16 x i8> @load_splat_v16i8_with_unfolded_gep_negative_offset(i8* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const -1
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v8x16.load_splat 0
+; CHECK-NEXT: v128.load8_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds i8, i8* %p, i32 -1
%e = load i8, i8* %s
@@ -142,7 +142,7 @@ define <16 x i8> @load_splat_v16i8_with_unfolded_offset(i8* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v8x16.load_splat 0
+; CHECK-NEXT: v128.load8_splat 0
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint i8* %p to i32
%r = add nsw i32 %q, 16
@@ -174,7 +174,7 @@ define <16 x i8> @load_splat_v16i8_with_unfolded_gep_offset(i8* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 1
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v8x16.load_splat 0
+; CHECK-NEXT: v128.load8_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr i8, i8* %p, i32 1
%e = load i8, i8* %s
@@ -200,7 +200,7 @@ define <16 x i8> @load_splat_v16i8_from_numeric_address() {
; CHECK: .functype load_splat_v16i8_from_numeric_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v8x16.load_splat 32
+; CHECK-NEXT: v128.load8_splat 32
; CHECK-NEXT: # fallthrough-return
%s = inttoptr i32 32 to i8*
%e = load i8, i8* %s
@@ -227,7 +227,7 @@ define <16 x i8> @load_splat_v16i8_from_global_address() {
; CHECK: .functype load_splat_v16i8_from_global_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v8x16.load_splat gv_i8
+; CHECK-NEXT: v128.load8_splat gv_i8
; CHECK-NEXT: # fallthrough-return
%e = load i8, i8* @gv_i8
%v1 = insertelement <16 x i8> undef, i8 %e, i32 0
@@ -366,7 +366,7 @@ define <8 x i16> @load_splat_v8i16(i16* %p) {
; CHECK: .functype load_splat_v8i16 (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v16x8.load_splat 0
+; CHECK-NEXT: v128.load16_splat 0
; CHECK-NEXT: # fallthrough-return
%e = load i16, i16* %p
%v1 = insertelement <8 x i16> undef, i16 %e, i32 0
@@ -428,7 +428,7 @@ define <8 x i16> @load_splat_v8i16_with_folded_offset(i16* %p) {
; CHECK: .functype load_splat_v8i16_with_folded_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v16x8.load_splat 16
+; CHECK-NEXT: v128.load16_splat 16
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint i16* %p to i32
%r = add nuw i32 %q, 16
@@ -500,7 +500,7 @@ define <8 x i16> @load_splat_v8i16_with_folded_gep_offset(i16* %p) {
; CHECK: .functype load_splat_v8i16_with_folded_gep_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v16x8.load_splat 2
+; CHECK-NEXT: v128.load16_splat 2
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds i16, i16* %p, i32 1
%e = load i16, i16* %s
@@ -568,7 +568,7 @@ define <8 x i16> @load_splat_v8i16_with_unfolded_gep_negative_offset(i16* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const -2
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v16x8.load_splat 0
+; CHECK-NEXT: v128.load16_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds i16, i16* %p, i32 -1
%e = load i16, i16* %s
@@ -644,7 +644,7 @@ define <8 x i16> @load_splat_v8i16_with_unfolded_offset(i16* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v16x8.load_splat 0
+; CHECK-NEXT: v128.load16_splat 0
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint i16* %p to i32
%r = add nsw i32 %q, 16
@@ -726,7 +726,7 @@ define <8 x i16> @load_splat_v8i16_with_unfolded_gep_offset(i16* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 2
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v16x8.load_splat 0
+; CHECK-NEXT: v128.load16_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr i16, i16* %p, i32 1
%e = load i16, i16* %s
@@ -796,7 +796,7 @@ define <8 x i16> @load_splat_v8i16_from_numeric_address() {
; CHECK: .functype load_splat_v8i16_from_numeric_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v16x8.load_splat 32
+; CHECK-NEXT: v128.load16_splat 32
; CHECK-NEXT: # fallthrough-return
%s = inttoptr i32 32 to i16*
%e = load i16, i16* %s
@@ -861,7 +861,7 @@ define <8 x i16> @load_splat_v8i16_from_global_address() {
; CHECK: .functype load_splat_v8i16_from_global_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v16x8.load_splat gv_i16
+; CHECK-NEXT: v128.load16_splat gv_i16
; CHECK-NEXT: # fallthrough-return
%e = load i16, i16* @gv_i16
%v1 = insertelement <8 x i16> undef, i16 %e, i32 0
@@ -1197,7 +1197,7 @@ define <4 x i32> @load_splat_v4i32(i32* %addr) {
; CHECK: .functype load_splat_v4i32 (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v32x4.load_splat 0
+; CHECK-NEXT: v128.load32_splat 0
; CHECK-NEXT: # fallthrough-return
%e = load i32, i32* %addr, align 4
%v1 = insertelement <4 x i32> undef, i32 %e, i32 0
@@ -1259,7 +1259,7 @@ define <4 x i32> @load_splat_v4i32_with_folded_offset(i32* %p) {
; CHECK: .functype load_splat_v4i32_with_folded_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v32x4.load_splat 16
+; CHECK-NEXT: v128.load32_splat 16
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint i32* %p to i32
%r = add nuw i32 %q, 16
@@ -1331,7 +1331,7 @@ define <4 x i32> @load_splat_v4i32_with_folded_gep_offset(i32* %p) {
; CHECK: .functype load_splat_v4i32_with_folded_gep_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v32x4.load_splat 4
+; CHECK-NEXT: v128.load32_splat 4
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds i32, i32* %p, i32 1
%e = load i32, i32* %s
@@ -1399,7 +1399,7 @@ define <4 x i32> @load_splat_v4i32_with_unfolded_gep_negative_offset(i32* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const -4
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v32x4.load_splat 0
+; CHECK-NEXT: v128.load32_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds i32, i32* %p, i32 -1
%e = load i32, i32* %s
@@ -1475,7 +1475,7 @@ define <4 x i32> @load_splat_v4i32_with_unfolded_offset(i32* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v32x4.load_splat 0
+; CHECK-NEXT: v128.load32_splat 0
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint i32* %p to i32
%r = add nsw i32 %q, 16
@@ -1557,7 +1557,7 @@ define <4 x i32> @load_splat_v4i32_with_unfolded_gep_offset(i32* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 4
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v32x4.load_splat 0
+; CHECK-NEXT: v128.load32_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr i32, i32* %p, i32 1
%e = load i32, i32* %s
@@ -1627,7 +1627,7 @@ define <4 x i32> @load_splat_v4i32_from_numeric_address() {
; CHECK: .functype load_splat_v4i32_from_numeric_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v32x4.load_splat 32
+; CHECK-NEXT: v128.load32_splat 32
; CHECK-NEXT: # fallthrough-return
%s = inttoptr i32 32 to i32*
%e = load i32, i32* %s
@@ -1692,7 +1692,7 @@ define <4 x i32> @load_splat_v4i32_from_global_address() {
; CHECK: .functype load_splat_v4i32_from_global_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v32x4.load_splat gv_i32
+; CHECK-NEXT: v128.load32_splat gv_i32
; CHECK-NEXT: # fallthrough-return
%e = load i32, i32* @gv_i32
%v1 = insertelement <4 x i32> undef, i32 %e, i32 0
@@ -2027,7 +2027,7 @@ define <2 x i64> @load_splat_v2i64(i64* %p) {
; CHECK: .functype load_splat_v2i64 (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v64x2.load_splat 0
+; CHECK-NEXT: v128.load64_splat 0
; CHECK-NEXT: # fallthrough-return
%e = load i64, i64* %p
%v1 = insertelement <2 x i64> undef, i64 %e, i32 0
@@ -2089,7 +2089,7 @@ define <2 x i64> @load_splat_v2i64_with_folded_offset(i64* %p) {
; CHECK: .functype load_splat_v2i64_with_folded_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v64x2.load_splat 16
+; CHECK-NEXT: v128.load64_splat 16
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint i64* %p to i32
%r = add nuw i32 %q, 16
@@ -2161,7 +2161,7 @@ define <2 x i64> @load_splat_v2i64_with_folded_gep_offset(i64* %p) {
; CHECK: .functype load_splat_v2i64_with_folded_gep_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v64x2.load_splat 8
+; CHECK-NEXT: v128.load64_splat 8
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds i64, i64* %p, i32 1
%e = load i64, i64* %s
@@ -2229,7 +2229,7 @@ define <2 x i64> @load_splat_v2i64_with_unfolded_gep_negative_offset(i64* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const -8
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v64x2.load_splat 0
+; CHECK-NEXT: v128.load64_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds i64, i64* %p, i32 -1
%e = load i64, i64* %s
@@ -2305,7 +2305,7 @@ define <2 x i64> @load_splat_v2i64_with_unfolded_offset(i64* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v64x2.load_splat 0
+; CHECK-NEXT: v128.load64_splat 0
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint i64* %p to i32
%r = add nsw i32 %q, 16
@@ -2387,7 +2387,7 @@ define <2 x i64> @load_splat_v2i64_with_unfolded_gep_offset(i64* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 8
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v64x2.load_splat 0
+; CHECK-NEXT: v128.load64_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr i64, i64* %p, i32 1
%e = load i64, i64* %s
@@ -2457,7 +2457,7 @@ define <2 x i64> @load_splat_v2i64_from_numeric_address() {
; CHECK: .functype load_splat_v2i64_from_numeric_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v64x2.load_splat 32
+; CHECK-NEXT: v128.load64_splat 32
; CHECK-NEXT: # fallthrough-return
%s = inttoptr i32 32 to i64*
%e = load i64, i64* %s
@@ -2522,7 +2522,7 @@ define <2 x i64> @load_splat_v2i64_from_global_address() {
; CHECK: .functype load_splat_v2i64_from_global_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v64x2.load_splat gv_i64
+; CHECK-NEXT: v128.load64_splat gv_i64
; CHECK-NEXT: # fallthrough-return
%e = load i64, i64* @gv_i64
%v1 = insertelement <2 x i64> undef, i64 %e, i32 0
@@ -2697,7 +2697,7 @@ define <4 x float> @load_splat_v4f32(float* %p) {
; CHECK: .functype load_splat_v4f32 (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v32x4.load_splat 0
+; CHECK-NEXT: v128.load32_splat 0
; CHECK-NEXT: # fallthrough-return
%e = load float, float* %p
%v1 = insertelement <4 x float> undef, float %e, i32 0
@@ -2724,7 +2724,7 @@ define <4 x float> @load_splat_v4f32_with_folded_offset(float* %p) {
; CHECK: .functype load_splat_v4f32_with_folded_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v32x4.load_splat 16
+; CHECK-NEXT: v128.load32_splat 16
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint float* %p to i32
%r = add nuw i32 %q, 16
@@ -2752,7 +2752,7 @@ define <4 x float> @load_splat_v4f32_with_folded_gep_offset(float* %p) {
; CHECK: .functype load_splat_v4f32_with_folded_gep_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v32x4.load_splat 4
+; CHECK-NEXT: v128.load32_splat 4
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds float, float* %p, i32 1
%e = load float, float* %s
@@ -2782,7 +2782,7 @@ define <4 x float> @load_splat_v4f32_with_unfolded_gep_negative_offset(float* %p
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const -4
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v32x4.load_splat 0
+; CHECK-NEXT: v128.load32_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds float, float* %p, i32 -1
%e = load float, float* %s
@@ -2814,7 +2814,7 @@ define <4 x float> @load_splat_v4f32_with_unfolded_offset(float* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v32x4.load_splat 0
+; CHECK-NEXT: v128.load32_splat 0
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint float* %p to i32
%r = add nsw i32 %q, 16
@@ -2846,7 +2846,7 @@ define <4 x float> @load_splat_v4f32_with_unfolded_gep_offset(float* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 4
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v32x4.load_splat 0
+; CHECK-NEXT: v128.load32_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr float, float* %p, i32 1
%e = load float, float* %s
@@ -2872,7 +2872,7 @@ define <4 x float> @load_splat_v4f32_from_numeric_address() {
; CHECK: .functype load_splat_v4f32_from_numeric_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v32x4.load_splat 32
+; CHECK-NEXT: v128.load32_splat 32
; CHECK-NEXT: # fallthrough-return
%s = inttoptr i32 32 to float*
%e = load float, float* %s
@@ -2899,7 +2899,7 @@ define <4 x float> @load_splat_v4f32_from_global_address() {
; CHECK: .functype load_splat_v4f32_from_global_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v32x4.load_splat gv_f32
+; CHECK-NEXT: v128.load32_splat gv_f32
; CHECK-NEXT: # fallthrough-return
%e = load float, float* @gv_f32
%v1 = insertelement <4 x float> undef, float %e, i32 0
@@ -3038,7 +3038,7 @@ define <2 x double> @load_splat_v2f64(double* %p) {
; CHECK: .functype load_splat_v2f64 (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v64x2.load_splat 0
+; CHECK-NEXT: v128.load64_splat 0
; CHECK-NEXT: # fallthrough-return
%e = load double, double* %p
%v1 = insertelement <2 x double> undef, double %e, i32 0
@@ -3065,7 +3065,7 @@ define <2 x double> @load_splat_v2f64_with_folded_offset(double* %p) {
; CHECK: .functype load_splat_v2f64_with_folded_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v64x2.load_splat 16
+; CHECK-NEXT: v128.load64_splat 16
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint double* %p to i32
%r = add nuw i32 %q, 16
@@ -3093,7 +3093,7 @@ define <2 x double> @load_splat_v2f64_with_folded_gep_offset(double* %p) {
; CHECK: .functype load_splat_v2f64_with_folded_gep_offset (i32) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
-; CHECK-NEXT: v64x2.load_splat 8
+; CHECK-NEXT: v128.load64_splat 8
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds double, double* %p, i32 1
%e = load double, double* %s
@@ -3123,7 +3123,7 @@ define <2 x double> @load_splat_v2f64_with_unfolded_gep_negative_offset(double*
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const -8
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v64x2.load_splat 0
+; CHECK-NEXT: v128.load64_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr inbounds double, double* %p, i32 -1
%e = load double, double* %s
@@ -3155,7 +3155,7 @@ define <2 x double> @load_splat_v2f64_with_unfolded_offset(double* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v64x2.load_splat 0
+; CHECK-NEXT: v128.load64_splat 0
; CHECK-NEXT: # fallthrough-return
%q = ptrtoint double* %p to i32
%r = add nsw i32 %q, 16
@@ -3187,7 +3187,7 @@ define <2 x double> @load_splat_v2f64_with_unfolded_gep_offset(double* %p) {
; CHECK-NEXT: local.get 0
; CHECK-NEXT: i32.const 8
; CHECK-NEXT: i32.add
-; CHECK-NEXT: v64x2.load_splat 0
+; CHECK-NEXT: v128.load64_splat 0
; CHECK-NEXT: # fallthrough-return
%s = getelementptr double, double* %p, i32 1
%e = load double, double* %s
@@ -3213,7 +3213,7 @@ define <2 x double> @load_splat_v2f64_from_numeric_address() {
; CHECK: .functype load_splat_v2f64_from_numeric_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v64x2.load_splat 32
+; CHECK-NEXT: v128.load64_splat 32
; CHECK-NEXT: # fallthrough-return
%s = inttoptr i32 32 to double*
%e = load double, double* %s
@@ -3240,7 +3240,7 @@ define <2 x double> @load_splat_v2f64_from_global_address() {
; CHECK: .functype load_splat_v2f64_from_global_address () -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i32.const 0
-; CHECK-NEXT: v64x2.load_splat gv_f64
+; CHECK-NEXT: v128.load64_splat gv_f64
; CHECK-NEXT: # fallthrough-return
%e = load double, double* @gv_f64
%v1 = insertelement <2 x double> undef, double %e, i32 0
diff --git a/llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll b/llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
index 2473f0b27b7e..4582bc62216a 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
@@ -67,7 +67,7 @@ define <16 x i8> @shl_abs(<16 x i8> %v, i8 %a) {
; CHECK-NEXT: i8x16.splat $push1=, $1
; CHECK-NEXT: i8x16.splat $push0=, $2
; CHECK-NEXT: i8x16.add $push2=, $pop1, $pop0
-; CHECK-NEXT: v8x16.shuffle $push3=, $pop2, $0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i8x16.shuffle $push3=, $pop2, $0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK-NEXT: i8x16.abs $push101=, $pop3
; CHECK-NEXT: local.tee $push100=, $3=, $pop101
; CHECK-NEXT: i8x16.extract_lane_u $push9=, $pop100, 0
diff --git a/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll b/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
index b3e2db98861d..3e73b47c5a5b 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
@@ -21,7 +21,7 @@ define <4 x i32> @f32x4_splat(float %x) {
; CHECK-LABEL: not_a_vec:
; CHECK-NEXT: .functype not_a_vec (i64, i64) -> (v128){{$}}
; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $0{{$}}
-; CHECK-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $pop[[L1]], $2, 0, 1, 2, 3
+; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $pop[[L1]], $2, 0, 1, 2, 3
; CHECK-NEXT: return $pop[[R]]
define <4 x i32> @not_a_vec(i128 %x) {
%a = bitcast i128 %x to <4 x i32>
diff --git a/llvm/test/CodeGen/WebAssembly/simd.ll b/llvm/test/CodeGen/WebAssembly/simd.ll
index 25e647f07230..c8053293ebac 100644
--- a/llvm/test/CodeGen/WebAssembly/simd.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd.ll
@@ -202,9 +202,9 @@ define <16 x i8> @replace_zero_v16i8(<16 x i8> %v, i8 %x) {
}
; CHECK-LABEL: shuffle_v16i8:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
; SIMD128-SAME: 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
@@ -215,9 +215,9 @@ define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
}
; CHECK-LABEL: shuffle_undef_v16i8:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
@@ -472,9 +472,9 @@ define <8 x i16> @replace_zero_v8i16(<8 x i16> %v, i16 %x) {
}
; CHECK-LABEL: shuffle_v8i16:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
; SIMD128-SAME: 0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @shuffle_v8i16(<8 x i16> %x, <8 x i16> %y) {
@@ -484,9 +484,9 @@ define <8 x i16> @shuffle_v8i16(<8 x i16> %x, <8 x i16> %y) {
}
; CHECK-LABEL: shuffle_undef_v8i16:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_undef_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
; SIMD128-SAME: 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @shuffle_undef_v8i16(<8 x i16> %x, <8 x i16> %y) {
@@ -634,9 +634,9 @@ define <4 x i32> @replace_zero_v4i32(<4 x i32> %v, i32 %x) {
}
; CHECK-LABEL: shuffle_v4i32:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
; SIMD128-SAME: 0, 1, 2, 3, 20, 21, 22, 23, 8, 9, 10, 11, 28, 29, 30, 31{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @shuffle_v4i32(<4 x i32> %x, <4 x i32> %y) {
@@ -646,9 +646,9 @@ define <4 x i32> @shuffle_v4i32(<4 x i32> %x, <4 x i32> %y) {
}
; CHECK-LABEL: shuffle_undef_v4i32:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_undef_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
; SIMD128-SAME: 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @shuffle_undef_v4i32(<4 x i32> %x, <4 x i32> %y) {
@@ -785,9 +785,9 @@ define <2 x i64> @replace_zero_v2i64(<2 x i64> %v, i64 %x) {
}
; CHECK-LABEL: shuffle_v2i64:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @shuffle_v2i64(<2 x i64> %x, <2 x i64> %y) {
@@ -796,9 +796,9 @@ define <2 x i64> @shuffle_v2i64(<2 x i64> %x, <2 x i64> %y) {
}
; CHECK-LABEL: shuffle_undef_v2i64:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_undef_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
; SIMD128-SAME: 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @shuffle_undef_v2i64(<2 x i64> %x, <2 x i64> %y) {
@@ -934,9 +934,9 @@ define <4 x float> @replace_zero_v4f32(<4 x float> %v, float %x) {
}
; CHECK-LABEL: shuffle_v4f32:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
; SIMD128-SAME: 0, 1, 2, 3, 20, 21, 22, 23, 8, 9, 10, 11, 28, 29, 30, 31{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x float> @shuffle_v4f32(<4 x float> %x, <4 x float> %y) {
@@ -946,9 +946,9 @@ define <4 x float> @shuffle_v4f32(<4 x float> %x, <4 x float> %y) {
}
; CHECK-LABEL: shuffle_undef_v4f32:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_undef_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
; SIMD128-SAME: 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x float> @shuffle_undef_v4f32(<4 x float> %x, <4 x float> %y) {
@@ -1085,9 +1085,9 @@ define <2 x double> @replace_zero_v2f64(<2 x double> %v, double %x) {
}
; CHECK-LABEL: shuffle_v2f64:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x double> @shuffle_v2f64(<2 x double> %x, <2 x double> %y) {
@@ -1097,9 +1097,9 @@ define <2 x double> @shuffle_v2f64(<2 x double> %x, <2 x double> %y) {
}
; CHECK-LABEL: shuffle_undef_v2f64:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .functype shuffle_undef_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
; SIMD128-SAME: 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x double> @shuffle_undef_v2f64(<2 x double> %x, <2 x double> %y) {
diff --git a/llvm/test/MC/Disassembler/WebAssembly/wasm.txt b/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
index bb50b646ab54..8201213e54b2 100644
--- a/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
+++ b/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
@@ -36,7 +36,7 @@
# CHECK: v128.const 50462976, 117835012, 185207048, 252579084
0xFD 0x0C 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
-# CHECK: v8x16.shuffle 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+# CHECK: i8x16.shuffle 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
0xFD 0x0D 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
# Check LEB128 encoding of SIMD instructions
diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s
index 509f4246475f..91e1f07fe44c 100644
--- a/llvm/test/MC/WebAssembly/simd-encodings.s
+++ b/llvm/test/MC/WebAssembly/simd-encodings.s
@@ -24,17 +24,17 @@ main:
# CHECK: i64x2.load32x2_u 32 # encoding: [0xfd,0x06,0x03,0x20]
i64x2.load32x2_u 32
- # CHECK: v8x16.load_splat 48 # encoding: [0xfd,0x07,0x00,0x30]
- v8x16.load_splat 48
+ # CHECK: v128.load8_splat 48 # encoding: [0xfd,0x07,0x00,0x30]
+ v128.load8_splat 48
- # CHECK: v16x8.load_splat 48 # encoding: [0xfd,0x08,0x01,0x30]
- v16x8.load_splat 48
+ # CHECK: v128.load16_splat 48 # encoding: [0xfd,0x08,0x01,0x30]
+ v128.load16_splat 48
- # CHECK: v32x4.load_splat 48 # encoding: [0xfd,0x09,0x02,0x30]
- v32x4.load_splat 48
+ # CHECK: v128.load32_splat 48 # encoding: [0xfd,0x09,0x02,0x30]
+ v128.load32_splat 48
- # CHECK: v64x2.load_splat 48 # encoding: [0xfd,0x0a,0x03,0x30]
- v64x2.load_splat 48
+ # CHECK: v128.load64_splat 48 # encoding: [0xfd,0x0a,0x03,0x30]
+ v128.load64_splat 48
# CHECK: v128.store 48 # encoding: [0xfd,0x0b,0x04,0x30]
v128.store 48
@@ -66,15 +66,15 @@ main:
# CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
v128.const 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783
- # CHECK: v8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23,
+ # CHECK: i8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23,
# CHECK-SAME: 8, 25, 10, 27, 12, 29, 14, 31
# CHECK-SAME: # encoding: [0xfd,0x0d,
# CHECK-SAME: 0x00,0x11,0x02,0x13,0x04,0x15,0x06,0x17,
# CHECK-SAME: 0x08,0x19,0x0a,0x1b,0x0c,0x1d,0x0e,0x1f]
- v8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31
+ i8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31
- # CHECK: v8x16.swizzle # encoding: [0xfd,0x0e]
- v8x16.swizzle
+ # CHECK: i8x16.swizzle # encoding: [0xfd,0x0e]
+ i8x16.swizzle
# CHECK: i8x16.splat # encoding: [0xfd,0x0f]
i8x16.splat
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