[llvm-branch-commits] [llvm] e18734f - [RISCV] Use more precise type constraints for the vmv.v.v and vmv.v.x intrinsics.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-12-21T16:27:09-08:00
New Revision: e18734f87a6eb8d2fbd2d9c6690b99b057953935

URL: https://github.com/llvm/llvm-project/commit/e18734f87a6eb8d2fbd2d9c6690b99b057953935
DIFF: https://github.com/llvm/llvm-project/commit/e18734f87a6eb8d2fbd2d9c6690b99b057953935.diff

LOG: [RISCV] Use more precise type constraints for the vmv.v.v and vmv.v.x intrinsics.

We can infer the input type from the result type. For vmv.v.v its
the same. For vmv.v.x its the element type.

Added: 
    

Modified: 
    llvm/include/llvm/IR/IntrinsicsRISCV.td

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index f65f8e6ab779..560f16afcc52 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -294,14 +294,6 @@ let TargetPrefix = "riscv" in {
     let ExtendOperand = 3;
   }
 
-  // For vmv.v.v, vmv.v.x, vmv.v.i
-  // Input: (vector_in/scalar_in, vl)
-  class RISCVUnary : Intrinsic<[llvm_anyvector_ty],
-                               [llvm_any_ty, llvm_anyint_ty],
-                               [IntrNoMem] >, RISCVVIntrinsic {
-    let ExtendOperand = 1;
-  }
-
   class RISCVTernaryAAAXNoMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
@@ -440,8 +432,14 @@ let TargetPrefix = "riscv" in {
   defm vssubu : RISCVSaturatingBinaryAAX;
   defm vssub : RISCVSaturatingBinaryAAX;
 
-  def int_riscv_vmv_v_v : RISCVUnary;
-  def int_riscv_vmv_v_x : RISCVUnary;
+  def int_riscv_vmv_v_v : Intrinsic<[llvm_anyvector_ty],
+                                    [LLVMMatchType<0>, llvm_anyint_ty],
+                                    [IntrNoMem]>, RISCVVIntrinsic;
+  def int_riscv_vmv_v_x : Intrinsic<[llvm_anyint_ty],
+                                    [LLVMVectorElementType<0>, llvm_anyint_ty],
+                                    [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 1;
+  }
 
   def int_riscv_vmv_x_s : Intrinsic<[LLVMVectorElementType<0>],
                                     [llvm_anyint_ty],