[llvm-branch-commits] [llvm] c60a58f - [InstCombine] Add check of i1 types in select-to-zext/sext transformation

[via llvm-branch-commits]

Author: Congzhe Cao
Date: 2020-12-21T18:46:24-05:00
New Revision: c60a58f8d4354ca1a6915045774bf98cfada8ef4

URL: https://github.com/llvm/llvm-project/commit/c60a58f8d4354ca1a6915045774bf98cfada8ef4
DIFF: https://github.com/llvm/llvm-project/commit/c60a58f8d4354ca1a6915045774bf98cfada8ef4.diff

LOG: [InstCombine] Add check of i1 types in select-to-zext/sext transformation

When doing select-to-zext/sext transformations, we should
not handle TrueVal and FalseVal of i1 type otherwise it
would result in zext/sext i1 to i1.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D93272

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

Removed: 
    


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diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index e05fa4ffa403..fe21f300a417 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -2606,7 +2606,10 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
   // select i1 %c, <2 x i8> <1, 1>, <2 x i8> <0, 0>
   // because that may need 3 instructions to splat the condition value:
   // extend, insertelement, shufflevector.
-  if (SelType->isIntOrIntVectorTy() &&
+  //
+  // Do not handle i1 TrueVal and FalseVal otherwise would result in
+  // zext/sext i1 to i1.
+  if (SelType->isIntOrIntVectorTy() && !SelType->isIntOrIntVectorTy(1) &&
       CondVal->getType()->isVectorTy() == SelType->isVectorTy()) {
     // select C, 1, 0 -> zext C to int
     if (match(TrueVal, m_One()) && match(FalseVal, m_Zero()))