[llvm-branch-commits] [llvm] 7948cd1 - [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.

[Fraser Cormack via llvm-branch-commits]

Author: Fraser Cormack
Date: 2020-12-18T21:50:55Z
New Revision: 7948cd11d17bea2d8679b9898d9debdcec5c11be

URL: https://github.com/llvm/llvm-project/commit/7948cd11d17bea2d8679b9898d9debdcec5c11be
DIFF: https://github.com/llvm/llvm-project/commit/7948cd11d17bea2d8679b9898d9debdcec5c11be.diff

LOG: [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    llvm/lib/Target/RISCV/RISCVTargetMachine.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 5e1b623db056..fe352296fb73 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -35,7 +35,7 @@ using namespace llvm;
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
-  auto PR = PassRegistry::getPassRegistry();
+  auto *PR = PassRegistry::getPassRegistry();
   initializeGlobalISel(*PR);
   initializeRISCVMergeBaseOffsetOptPass(*PR);
   initializeRISCVExpandPseudoPass(*PR);
@@ -43,12 +43,10 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
 }
 
 static StringRef computeDataLayout(const Triple &TT) {
-  if (TT.isArch64Bit()) {
+  if (TT.isArch64Bit())
     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
-  } else {
-    assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
-    return "e-m:e-p:32:32-i64:64-n32-S128";
-  }
+  assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
+  return "e-m:e-p:32:32-i64:64-n32-S128";
 }
 
 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
@@ -143,7 +141,7 @@ class RISCVPassConfig : public TargetPassConfig {
   void addPreSched2() override;
   void addPreRegAlloc() override;
 };
-}
+} // namespace
 
 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new RISCVPassConfig(*this, PM);

diff  --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index 9d1e04a42f72..3156333f7ee1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -47,6 +47,6 @@ class RISCVTargetMachine : public LLVMTargetMachine {
   virtual bool isNoopAddrSpaceCast(unsigned SrcAS,
                                    unsigned DstAS) const override;
 };
-}
+} // namespace llvm
 
 #endif