[llvm-branch-commits] [llvm] 42b92b3 - [ARM][AArch64] Adding basic support for the v8.7-A architecture
Lucas Prates via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Dec 17 05:49:26 PST 2020
Author: Lucas Prates
Date: 2020-12-17T13:45:08Z
New Revision: 42b92b31b8b8ee9fdcd68adfe57db11561a5edcd
URL: https://github.com/llvm/llvm-project/commit/42b92b31b8b8ee9fdcd68adfe57db11561a5edcd
DIFF: https://github.com/llvm/llvm-project/commit/42b92b31b8b8ee9fdcd68adfe57db11561a5edcd.diff
LOG: [ARM][AArch64] Adding basic support for the v8.7-A architecture
This introduces support for the v8.7-A architecture through a new
subtarget feature called "v8.7a". It adds two new "WFET" and "WFIT"
instructions, the nXS limited-TLB-maintenance qualifier for DSB and TLBI
instructions, a new CPU id register, ID_AA64ISAR2_EL1, and the new
HCRX_EL2 system register.
Based on patches written by Simon Tatham and Victor Campos.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D91772
Added:
llvm/test/MC/AArch64/armv8.7a-hcx.s
llvm/test/MC/AArch64/armv8.7a-wfxt.s
llvm/test/MC/AArch64/armv8.7a-xs.s
llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
Modified:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/test/MC/AArch64/arm64-system-encoding.s
llvm/test/MC/AArch64/basic-a64-diagnostics.s
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 5bafe430a1b4..fd7894aa3fcb 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -400,6 +400,15 @@ def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
"true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
+def FeatureXS : SubtargetFeature<"xs", "HasXS",
+ "true", "Enable Armv8.7-A limited-TLB-maintenance instruction">;
+
+def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
+ "true", "Enable Armv8.7-A WFET and WFIT instruction">;
+
+def FeatureHCX : SubtargetFeature<
+ "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
+
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;
@@ -440,6 +449,10 @@ def HasV8_6aOps : SubtargetFeature<
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
+def HasV8_7aOps : SubtargetFeature<
+ "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
+ [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
+
def HasV8_0rOps : SubtargetFeature<
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
[//v8.1
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 0f6ae93742bf..3c19a5bad573 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1297,8 +1297,9 @@ class SimpleSystemI<bit L, dag iops, string asm, string operands,
}
// System instructions which have an Rt register.
-class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
- : BaseSystemI<L, oops, iops, asm, operands>,
+class RtSystemI<bit L, dag oops, dag iops, string asm, string operands,
+ list<dag> pattern = []>
+ : BaseSystemI<L, oops, iops, asm, operands, pattern>,
Sched<[WriteSys]> {
bits<5> Rt;
let Inst{4-0} = Rt;
@@ -1326,6 +1327,16 @@ class TMSystemI<bits<4> CRm, string asm, list<dag> pattern>
let Inst{4-0} = Rt;
}
+// System instructions that pass a register argument
+// This class assumes the register is for input rather than output.
+class RegInputSystemI<bits<4> CRm, bits<3> Op2, string asm,
+ list<dag> pattern = []>
+ : RtSystemI<0, (outs), (ins GPR64:$Rt), asm, "\t$Rt", pattern> {
+ let Inst{20-12} = 0b000110001;
+ let Inst{11-8} = CRm;
+ let Inst{7-5} = Op2;
+}
+
// System instructions for transactional memory - no operand
class TMSystemINoOperand<bits<4> CRm, string asm, list<dag> pattern>
: TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
@@ -1366,6 +1377,14 @@ def barrier_op : Operand<i32> {
let PrintMethod = "printBarrierOption";
let ParserMatchClass = BarrierAsmOperand;
}
+def BarriernXSAsmOperand : AsmOperandClass {
+ let Name = "BarriernXS";
+ let ParserMethod = "tryParseBarriernXSOperand";
+}
+def barrier_nxs_op : Operand<i32> {
+ let PrintMethod = "printBarriernXSOption";
+ let ParserMatchClass = BarriernXSAsmOperand;
+}
class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
list<dag> pattern = []>
: SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 28ab67599c48..d366c3c4d04c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -25,6 +25,8 @@ def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">,
AssemblerPredicate<(all_of HasV8_5aOps), "armv8.5a">;
def HasV8_6a : Predicate<"Subtarget->hasV8_6aOps()">,
AssemblerPredicate<(all_of HasV8_6aOps), "armv8.6a">;
+def HasV8_7a : Predicate<"Subtarget->hasV8_7aOps()">,
+ AssemblerPredicate<(all_of HasV8_7aOps), "armv8.7a">;
def HasVH : Predicate<"Subtarget->hasVH()">,
AssemblerPredicate<(all_of FeatureVH), "vh">;
@@ -149,6 +151,10 @@ def HasMatMulFP32 : Predicate<"Subtarget->hasMatMulFP32()">,
AssemblerPredicate<(all_of FeatureMatMulFP32), "f32mm">;
def HasMatMulFP64 : Predicate<"Subtarget->hasMatMulFP64()">,
AssemblerPredicate<(all_of FeatureMatMulFP64), "f64mm">;
+def HasXS : Predicate<"Subtarget->hasXS()">,
+ AssemblerPredicate<(all_of FeatureXS), "xs">;
+def HasWFxT : Predicate<"Subtarget->hasWFxT()">,
+ AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@@ -789,6 +795,18 @@ def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> {
let Inst{12} = 0;
let Predicates = [HasTRACEV8_4];
}
+
+def DSBnXS : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> {
+ let CRm{1-0} = 0b11;
+ let Inst{9-8} = 0b10;
+ let Predicates = [HasXS];
+}
+
+let Predicates = [HasWFxT] in {
+def WFET : RegInputSystemI<0b0000, 0b000, "wfet">;
+def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">;
+}
+
}
// ARMv8.2-A Dot Product
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 7795cfce6c54..575542d1b6aa 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -86,6 +86,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool HasV8_4aOps = false;
bool HasV8_5aOps = false;
bool HasV8_6aOps = false;
+ bool HasV8_7aOps = false;
bool HasV8_0rOps = false;
bool HasCONTEXTIDREL2 = false;
@@ -167,6 +168,11 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool HasFineGrainedTraps = false;
bool HasEnhancedCounterVirtualization = false;
+ // Armv8.7-A Extensions
+ bool HasXS = false;
+ bool HasWFxT = false;
+ bool HasHCX = false;
+
// Arm SVE2 extensions
bool HasSVE2 = false;
bool HasSVE2AES = false;
@@ -494,6 +500,9 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool hasTRACEV8_4() const { return HasTRACEV8_4; }
bool hasAM() const { return HasAM; }
bool hasAMVS() const { return HasAMVS; }
+ bool hasXS() const { return HasXS; }
+ bool hasWFxT() const { return HasWFxT; }
+ bool hasHCX() const { return HasHCX; }
bool hasSEL2() const { return HasSEL2; }
bool hasPMU() const { return HasPMU; }
bool hasTLB_RMI() const { return HasTLB_RMI; }
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 699fd36be251..229ea0e9090d 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -98,6 +98,21 @@ def : DB<"ld", 0xd>;
def : DB<"st", 0xe>;
def : DB<"sy", 0xf>;
+class DBnXS<string name, bits<4> encoding, bits<5> immValue> : SearchableTable {
+ let SearchableFields = ["Name", "Encoding", "ImmValue"];
+ let EnumValueField = "Encoding";
+
+ string Name = name;
+ bits<4> Encoding = encoding;
+ bits<5> ImmValue = immValue;
+ code Requires = [{ {AArch64::FeatureXS} }];
+}
+
+def : DBnXS<"oshnxs", 0x3, 0x10>;
+def : DBnXS<"nshnxs", 0x7, 0x14>;
+def : DBnXS<"ishnxs", 0xb, 0x18>;
+def : DBnXS<"synxs", 0xf, 0x1c>;
+
//===----------------------------------------------------------------------===//
// DC (data cache maintenance) instruction options.
//===----------------------------------------------------------------------===//
@@ -389,11 +404,8 @@ def : BTI<"jc", 0b11>;
// TLBI (translation lookaside buffer invalidate) instruction options.
//===----------------------------------------------------------------------===//
-class TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm,
- bits<3> op2, bit needsreg = 1> : SearchableTable {
- let SearchableFields = ["Name", "Encoding"];
- let EnumValueField = "Encoding";
-
+class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, bit needsreg> {
string Name = name;
bits<14> Encoding;
let Encoding{13-11} = op1;
@@ -401,95 +413,122 @@ class TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm,
let Encoding{6-3} = crm;
let Encoding{2-0} = op2;
bit NeedsReg = needsreg;
- code Requires = [{ {} }];
+ list<string> Requires = [];
+ list<string> ExtraRequires = [];
+ code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }];
}
-def : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
-def : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
-def : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>;
-def : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
-def : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>;
-def : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>;
-def : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
-def : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>;
-def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
-def : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>;
-def : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>;
-def : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>;
-def : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>;
-def : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>;
-def : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>;
-def : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>;
-def : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>;
-def : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>;
-def : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>;
-def : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>;
-def : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>;
-def : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>;
-def : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>;
-def : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>;
-def : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>;
-def : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>;
-def : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>;
-def : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>;
-def : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>;
-def : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>;
-def : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>;
-def : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>;
+def TLBITable : GenericTable {
+ let FilterClass = "TLBIEntry";
+ let CppTypeName = "TLBI";
+ let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];
+}
+
+def lookupTLBIByName : SearchIndex {
+ let Table = TLBITable;
+ let Key = ["Name"];
+}
+
+def lookupTLBIByEncoding : SearchIndex {
+ let Table = TLBITable;
+ let Key = ["Encoding"];
+}
+
+multiclass TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, bit needsreg = 1> {
+ def : TLBIEntry<name, op1, crn, crm, op2, needsreg>;
+ def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> {
+ let Encoding{7} = 1;
+ let ExtraRequires = ["AArch64::FeatureXS"];
+ }
+}
+
+defm : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
+defm : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
+defm : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>;
+defm : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
+defm : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>;
+defm : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>;
+defm : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
+defm : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>;
+defm : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
+defm : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>;
+defm : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>;
+defm : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>;
+defm : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>;
+defm : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>;
+defm : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>;
+defm : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>;
+defm : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>;
+defm : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>;
+defm : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>;
+defm : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>;
+defm : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>;
+defm : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>;
+defm : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>;
+defm : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>;
+defm : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>;
+defm : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>;
+defm : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>;
+defm : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>;
+defm : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>;
+defm : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>;
+defm : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>;
+defm : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>;
// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = [{ {AArch64::FeatureTLB_RMI} }] in {
+let Requires = ["AArch64::FeatureTLB_RMI"] in {
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
// op1 CRn CRm op2
-def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
-def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
-def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
-def : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>;
-def : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>;
-def : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>;
-def : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>;
-def : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>;
-def : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>;
-def : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>;
-def : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>;
-def : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>;
-def : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>;
-def : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>;
-def : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>;
-def : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>;
+defm : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
+defm : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
+defm : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
+defm : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>;
+defm : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>;
+defm : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>;
+defm : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>;
+defm : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>;
+defm : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>;
+defm : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>;
+defm : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>;
+defm : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>;
+defm : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>;
+defm : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>;
+defm : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>;
+defm : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>;
// Armv8.4-A TLB Range Maintenance instructions:
// op1 CRn CRm op2
-def : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>;
-def : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>;
-def : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>;
-def : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>;
-def : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>;
-def : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>;
-def : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>;
-def : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>;
-def : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>;
-def : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>;
-def : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>;
-def : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>;
-def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
-def : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>;
-def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
-def : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>;
-def : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>;
-def : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>;
-def : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>;
-def : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>;
-def : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>;
-def : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>;
-def : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>;
-def : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>;
-def : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>;
-def : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>;
-def : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>;
-def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;
-def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;
-def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;
+defm : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>;
+defm : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>;
+defm : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>;
+defm : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>;
+defm : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>;
+defm : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>;
+defm : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>;
+defm : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>;
+defm : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>;
+defm : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>;
+defm : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>;
+defm : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>;
+defm : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
+defm : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>;
+defm : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
+defm : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>;
+defm : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>;
+defm : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>;
+defm : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>;
+defm : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>;
+defm : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>;
+defm : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>;
+defm : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>;
+defm : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>;
+defm : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>;
+defm : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>;
+defm : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>;
+defm : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;
+defm : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;
+defm : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;
} //FeatureTLB_RMI
// Armv8.5-A Prediction Restriction by Context instruction options:
@@ -604,6 +643,7 @@ def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>;
def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>;
def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>;
def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;
+def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>;
def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;
def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;
def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>;
@@ -819,6 +859,9 @@ def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>;
def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>;
def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>;
def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>;
+def : RWSysReg<"HCRX_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b010> {
+ let Requires = [{ {AArch64::FeatureHCX} }];
+}
def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>;
def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>;
def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index f3514f1d47f7..6a251f0d346c 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -230,6 +230,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
RegKind MatchKind);
OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
+ OperandMatchResultTy tryParseBarriernXSOperand(OperandVector &Operands);
OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
@@ -401,6 +402,7 @@ class AArch64Operand : public MCParsedAsmOperand {
const char *Data;
unsigned Length;
unsigned Val; // Not the enum since not all values have names.
+ bool HasnXSModifier;
};
struct SysRegOp {
@@ -570,6 +572,11 @@ class AArch64Operand : public MCParsedAsmOperand {
return StringRef(Barrier.Data, Barrier.Length);
}
+ bool getBarriernXSModifier() const {
+ assert(Kind == k_Barrier && "Invalid access!");
+ return Barrier.HasnXSModifier;
+ }
+
unsigned getReg() const override {
assert(Kind == k_Register && "Invalid access!");
return Reg.RegNum;
@@ -1031,7 +1038,12 @@ class AArch64Operand : public MCParsedAsmOperand {
AArch64_AM::getFP64Imm(getFPImm().bitcastToAPInt()) != -1;
}
- bool isBarrier() const { return Kind == k_Barrier; }
+ bool isBarrier() const {
+ return Kind == k_Barrier && !getBarriernXSModifier();
+ }
+ bool isBarriernXS() const {
+ return Kind == k_Barrier && getBarriernXSModifier();
+ }
bool isSysReg() const { return Kind == k_SysReg; }
bool isMRSSystemRegister() const {
@@ -1721,6 +1733,11 @@ class AArch64Operand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createImm(getBarrier()));
}
+ void addBarriernXSOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createImm(getBarrier()));
+ }
+
void addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -1956,11 +1973,13 @@ class AArch64Operand : public MCParsedAsmOperand {
static std::unique_ptr<AArch64Operand> CreateBarrier(unsigned Val,
StringRef Str,
SMLoc S,
- MCContext &Ctx) {
+ MCContext &Ctx,
+ bool HasnXSModifier) {
auto Op = std::make_unique<AArch64Operand>(k_Barrier, Ctx);
Op->Barrier.Val = Val;
Op->Barrier.Data = Str.data();
Op->Barrier.Length = Str.size();
+ Op->Barrier.HasnXSModifier = HasnXSModifier;
Op->StartLoc = S;
Op->EndLoc = S;
return Op;
@@ -2886,6 +2905,7 @@ static const struct Extension {
{"sve2-sm4", {AArch64::FeatureSVE2SM4}},
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
+ {"xs", {AArch64::FeatureXS}},
// FIXME: Unsupported extensions
{"pan", {}},
{"lor", {}},
@@ -2906,6 +2926,8 @@ static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
Str += "ARMv8.5a";
else if (FBS[AArch64::HasV8_6aOps])
Str += "ARMv8.6a";
+ else if (FBS[AArch64::HasV8_7aOps])
+ Str += "ARMv8.7a";
else {
SmallVector<std::string, 2> ExtMatches;
for (const auto& Ext : ExtensionMap) {
@@ -3043,11 +3065,11 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
if (Mnemonic == "tsb" && Tok.isNot(AsmToken::Identifier)) {
TokError("'csync' operand expected");
return MatchOperand_ParseFail;
- // Can be either a #imm style literal or an option name
} else if (parseOptionalToken(AsmToken::Hash) || Tok.is(AsmToken::Integer)) {
// Immediate operand.
const MCExpr *ImmVal;
SMLoc ExprLoc = getLoc();
+ AsmToken IntTok = Tok;
if (getParser().parseExpression(ImmVal))
return MatchOperand_ParseFail;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
@@ -3055,13 +3077,22 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
Error(ExprLoc, "immediate value expected for barrier operand");
return MatchOperand_ParseFail;
}
- if (MCE->getValue() < 0 || MCE->getValue() > 15) {
+ int64_t Value = MCE->getValue();
+ if (Mnemonic == "dsb" && Value > 15) {
+ // This case is a no match here, but it might be matched by the nXS
+ // variant. Deliberately not unlex the optional '#' as it is not necessary
+ // to characterize an integer immediate.
+ Parser.getLexer().UnLex(IntTok);
+ return MatchOperand_NoMatch;
+ }
+ if (Value < 0 || Value > 15) {
Error(ExprLoc, "barrier operand out of range");
return MatchOperand_ParseFail;
}
- auto DB = AArch64DB::lookupDBByEncoding(MCE->getValue());
- Operands.push_back(AArch64Operand::CreateBarrier(
- MCE->getValue(), DB ? DB->Name : "", ExprLoc, getContext()));
+ auto DB = AArch64DB::lookupDBByEncoding(Value);
+ Operands.push_back(AArch64Operand::CreateBarrier(Value, DB ? DB->Name : "",
+ ExprLoc, getContext(),
+ false /*hasnXSModifier*/));
return MatchOperand_Success;
}
@@ -3070,9 +3101,10 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
return MatchOperand_ParseFail;
}
- auto TSB = AArch64TSB::lookupTSBByName(Tok.getString());
+ StringRef Operand = Tok.getString();
+ auto TSB = AArch64TSB::lookupTSBByName(Operand);
+ auto DB = AArch64DB::lookupDBByName(Operand);
// The only valid named option for ISB is 'sy'
- auto DB = AArch64DB::lookupDBByName(Tok.getString());
if (Mnemonic == "isb" && (!DB || DB->Encoding != AArch64DB::sy)) {
TokError("'sy' or #imm operand expected");
return MatchOperand_ParseFail;
@@ -3081,12 +3113,73 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
TokError("'csync' operand expected");
return MatchOperand_ParseFail;
} else if (!DB && !TSB) {
+ if (Mnemonic == "dsb") {
+ // This case is a no match here, but it might be matched by the nXS
+ // variant.
+ return MatchOperand_NoMatch;
+ }
TokError("invalid barrier option name");
return MatchOperand_ParseFail;
}
Operands.push_back(AArch64Operand::CreateBarrier(
- DB ? DB->Encoding : TSB->Encoding, Tok.getString(), getLoc(), getContext()));
+ DB ? DB->Encoding : TSB->Encoding, Tok.getString(), getLoc(),
+ getContext(), false /*hasnXSModifier*/));
+ Parser.Lex(); // Consume the option
+
+ return MatchOperand_Success;
+}
+
+OperandMatchResultTy
+AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
+ MCAsmParser &Parser = getParser();
+ const AsmToken &Tok = Parser.getTok();
+
+ assert(Mnemonic == "dsb" && "Instruction does not accept nXS operands");
+ if (Mnemonic != "dsb")
+ return MatchOperand_ParseFail;
+
+ if (parseOptionalToken(AsmToken::Hash) || Tok.is(AsmToken::Integer)) {
+ // Immediate operand.
+ const MCExpr *ImmVal;
+ SMLoc ExprLoc = getLoc();
+ if (getParser().parseExpression(ImmVal))
+ return MatchOperand_ParseFail;
+ const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
+ if (!MCE) {
+ Error(ExprLoc, "immediate value expected for barrier operand");
+ return MatchOperand_ParseFail;
+ }
+ int64_t Value = MCE->getValue();
+ // v8.7-A DSB in the nXS variant accepts only the following immediate
+ // values: 16, 20, 24, 28.
+ if (Value != 16 && Value != 20 && Value != 24 && Value != 28) {
+ Error(ExprLoc, "barrier operand out of range");
+ return MatchOperand_ParseFail;
+ }
+ auto DB = AArch64DBnXS::lookupDBnXSByImmValue(Value);
+ Operands.push_back(AArch64Operand::CreateBarrier(DB->Encoding, DB->Name,
+ ExprLoc, getContext(),
+ true /*hasnXSModifier*/));
+ return MatchOperand_Success;
+ }
+
+ if (Tok.isNot(AsmToken::Identifier)) {
+ TokError("invalid operand for instruction");
+ return MatchOperand_ParseFail;
+ }
+
+ StringRef Operand = Tok.getString();
+ auto DB = AArch64DBnXS::lookupDBnXSByName(Operand);
+
+ if (!DB) {
+ TokError("invalid barrier option name");
+ return MatchOperand_ParseFail;
+ }
+
+ Operands.push_back(
+ AArch64Operand::CreateBarrier(DB->Encoding, Tok.getString(), getLoc(),
+ getContext(), true /*hasnXSModifier*/));
Parser.Lex(); // Consume the option
return MatchOperand_Success;
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 67f6cf40a727..501817f90c45 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -849,7 +849,7 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
}
break;
}
- } else if (CnVal == 8) {
+ } else if (CnVal == 8 || CnVal == 9) {
// TLBI aliases
const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
@@ -1421,6 +1421,22 @@ void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
O << "#" << Val;
}
+void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ unsigned Val = MI->getOperand(OpNo).getImm();
+ assert(MI->getOpcode() == AArch64::DSBnXS);
+
+ StringRef Name;
+ auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
+ Name = DB ? DB->Name : "";
+
+ if (!Name.empty())
+ O << Name;
+ else
+ O << "#" << Val;
+}
+
void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
index 1a0342b783a2..21b7d4bca5f5 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
@@ -160,6 +160,8 @@ class AArch64InstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printBarrierOption(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
+ void printBarriernXSOption(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &O);
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum,
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
index c27fc7a112ec..ac59d73fd9fd 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
@@ -25,6 +25,13 @@ namespace llvm {
}
+namespace llvm {
+ namespace AArch64DBnXS {
+#define GET_DBNXS_IMPL
+#include "AArch64GenSystemOperands.inc"
+ }
+}
+
namespace llvm {
namespace AArch64DB {
#define GET_DB_IMPL
@@ -158,7 +165,7 @@ std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
namespace llvm {
namespace AArch64TLBI {
-#define GET_TLBI_IMPL
+#define GET_TLBITable_IMPL
#include "AArch64GenSystemOperands.inc"
}
}
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index c17158513cb8..1b13c94389cb 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -338,6 +338,14 @@ struct SysAliasReg : SysAlias {
: SysAlias(N, E, F), NeedsReg(R) {}
};
+struct SysAliasImm : SysAlias {
+ uint16_t ImmValue;
+ constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
+ : SysAlias(N, E), ImmValue(I) {}
+ constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
+ : SysAlias(N, E, F), ImmValue(I) {}
+};
+
namespace AArch64AT{
struct AT : SysAlias {
using SysAlias::SysAlias;
@@ -354,6 +362,14 @@ namespace AArch64DB {
#include "AArch64GenSystemOperands.inc"
}
+namespace AArch64DBnXS {
+ struct DBnXS : SysAliasImm {
+ using SysAliasImm::SysAliasImm;
+ };
+ #define GET_DBNXS_DECL
+ #include "AArch64GenSystemOperands.inc"
+}
+
namespace AArch64DC {
struct DC : SysAlias {
using SysAlias::SysAlias;
@@ -552,7 +568,7 @@ namespace AArch64TLBI {
struct TLBI : SysAliasReg {
using SysAliasReg::SysAliasReg;
};
- #define GET_TLBI_DECL
+ #define GET_TLBITable_DECL
#include "AArch64GenSystemOperands.inc"
}
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 91002b429f7a..695a53eec93e 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -165,6 +165,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool HasV8_4aOps = false;
bool HasV8_5aOps = false;
bool HasV8_6aOps = false;
+ bool HasV8_7aOps = false;
bool HasV8MBaselineOps = false;
bool HasV8MMainlineOps = false;
bool HasV8_1MMainlineOps = false;
@@ -596,6 +597,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool hasV8_4aOps() const { return HasV8_4aOps; }
bool hasV8_5aOps() const { return HasV8_5aOps; }
bool hasV8_6aOps() const { return HasV8_6aOps; }
+ bool hasV8_7aOps() const { return HasV8_7aOps; }
bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index ae34555dccda..bb363656a0a7 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -277,6 +277,7 @@ foo:
mrs x3, ID_AA64DFR1_EL1
mrs x3, ID_AA64ISAR0_EL1
mrs x3, ID_AA64ISAR1_EL1
+ mrs x3, ID_AA64ISAR2_EL1
mrs x3, ID_AA64MMFR0_EL1
mrs x3, ID_AA64MMFR1_EL1
mrs x3, ID_AA64PFR0_EL1
@@ -463,6 +464,7 @@ foo:
; CHECK: mrs x3, ID_AA64DFR1_EL1 ; encoding: [0x23,0x05,0x38,0xd5]
; CHECK: mrs x3, ID_AA64ISAR0_EL1 ; encoding: [0x03,0x06,0x38,0xd5]
; CHECK: mrs x3, ID_AA64ISAR1_EL1 ; encoding: [0x23,0x06,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64ISAR2_EL1 ; encoding: [0x43,0x06,0x38,0xd5]
; CHECK: mrs x3, ID_AA64MMFR0_EL1 ; encoding: [0x03,0x07,0x38,0xd5]
; CHECK: mrs x3, ID_AA64MMFR1_EL1 ; encoding: [0x23,0x07,0x38,0xd5]
; CHECK: mrs x3, ID_AA64PFR0_EL1 ; encoding: [0x03,0x04,0x38,0xd5]
diff --git a/llvm/test/MC/AArch64/armv8.7a-hcx.s b/llvm/test/MC/AArch64/armv8.7a-hcx.s
new file mode 100644
index 000000000000..d89d6af7b54b
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.7a-hcx.s
@@ -0,0 +1,12 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+hcx < %s 2>%t | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s 2>%t | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-HCX-ERR %s < %t
+
+ mrs x2, HCRX_EL2
+// CHECK: mrs x2, HCRX_EL2 // encoding: [0x42,0x12,0x3c,0xd5]
+// CHECK-NO-HCX-ERR: [[@LINE-2]]:11: error: expected readable system register
+
+ msr HCRX_EL2, x3
+// CHECK: msr HCRX_EL2, x3 // encoding: [0x43,0x12,0x1c,0xd5]
+// CHECK-NO-HCX-ERR: [[@LINE-2]]:7: error: expected writable system register
diff --git a/llvm/test/MC/AArch64/armv8.7a-wfxt.s b/llvm/test/MC/AArch64/armv8.7a-wfxt.s
new file mode 100644
index 000000000000..826153bda624
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.7a-wfxt.s
@@ -0,0 +1,12 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+wfxt < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-WFxT-ERR %s < %t
+
+ wfet x17
+// CHECK: wfet x17 // encoding: [0x11,0x10,0x03,0xd5]
+// CHECK-NO-WFxT-ERR: [[@LINE-2]]:3: error: instruction requires: wfxt
+
+ wfit x3
+// CHECK: wfit x3 // encoding: [0x23,0x10,0x03,0xd5]
+// CHECK-NO-WFxT-ERR: [[@LINE-2]]:3: error: instruction requires: wfxt
diff --git a/llvm/test/MC/AArch64/armv8.7a-xs.s b/llvm/test/MC/AArch64/armv8.7a-xs.s
new file mode 100644
index 000000000000..6193c1f15f53
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.7a-xs.s
@@ -0,0 +1,273 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,+xs < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-XS-ERR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-XS-ERR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-NO-XS-ERR %s < %t
+
+ dsb #16
+ dsb #20
+ dsb #24
+ dsb #28
+ dsb oshnxs
+ dsb nshnxs
+ dsb ishnxs
+ dsb synxs
+// CHECK: dsb oshnxs // encoding: [0x3f,0x32,0x03,0xd5]
+// CHECK: dsb nshnxs // encoding: [0x3f,0x36,0x03,0xd5]
+// CHECK: dsb ishnxs // encoding: [0x3f,0x3a,0x03,0xd5]
+// CHECK: dsb synxs // encoding: [0x3f,0x3e,0x03,0xd5]
+// CHECK: dsb oshnxs // encoding: [0x3f,0x32,0x03,0xd5]
+// CHECK: dsb nshnxs // encoding: [0x3f,0x36,0x03,0xd5]
+// CHECK: dsb ishnxs // encoding: [0x3f,0x3a,0x03,0xd5]
+// CHECK: dsb synxs // encoding: [0x3f,0x3e,0x03,0xd5]
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+
+ dsb #17
+ dsb nshstnxs
+// CHECK-ERR: [[@LINE-2]]:8: error: barrier operand out of range
+// CHECK-ERR: [[@LINE-2]]:7: error: invalid barrier option name
+
+ tlbi ipas2e1isnxs, x1
+ tlbi ipas2le1isnxs, x1
+ tlbi vmalle1isnxs
+ tlbi alle2isnxs
+ tlbi alle3isnxs
+ tlbi vae1isnxs, x1
+ tlbi vae2isnxs, x1
+ tlbi vae3isnxs, x1
+ tlbi aside1isnxs, x1
+ tlbi vaae1isnxs, x1
+ tlbi alle1isnxs
+ tlbi vale1isnxs, x1
+ tlbi vale2isnxs, x1
+ tlbi vale3isnxs, x1
+ tlbi vmalls12e1isnxs
+ tlbi vaale1isnxs, x1
+ tlbi ipas2e1nxs, x1
+ tlbi ipas2le1nxs, x1
+ tlbi vmalle1nxs
+ tlbi alle2nxs
+ tlbi alle3nxs
+ tlbi vae1nxs, x1
+ tlbi vae2nxs, x1
+ tlbi vae3nxs, x1
+ tlbi aside1nxs, x1
+ tlbi vaae1nxs, x1
+ tlbi alle1nxs
+ tlbi vale1nxs, x1
+ tlbi vale2nxs, x1
+ tlbi vale3nxs, x1
+ tlbi vmalls12e1nxs
+ tlbi vaale1nxs, x1
+// CHECK: tlbi ipas2e1isnxs, x1 // encoding: [0x21,0x90,0x0c,0xd5]
+// CHECK: tlbi ipas2le1isnxs, x1 // encoding: [0xa1,0x90,0x0c,0xd5]
+// CHECK: tlbi vmalle1isnxs // encoding: [0x1f,0x93,0x08,0xd5]
+// CHECK: tlbi alle2isnxs // encoding: [0x1f,0x93,0x0c,0xd5]
+// CHECK: tlbi alle3isnxs // encoding: [0x1f,0x93,0x0e,0xd5]
+// CHECK: tlbi vae1isnxs, x1 // encoding: [0x21,0x93,0x08,0xd5]
+// CHECK: tlbi vae2isnxs, x1 // encoding: [0x21,0x93,0x0c,0xd5]
+// CHECK: tlbi vae3isnxs, x1 // encoding: [0x21,0x93,0x0e,0xd5]
+// CHECK: tlbi aside1isnxs, x1 // encoding: [0x41,0x93,0x08,0xd5]
+// CHECK: tlbi vaae1isnxs, x1 // encoding: [0x61,0x93,0x08,0xd5]
+// CHECK: tlbi alle1isnxs // encoding: [0x9f,0x93,0x0c,0xd5]
+// CHECK: tlbi vale1isnxs, x1 // encoding: [0xa1,0x93,0x08,0xd5]
+// CHECK: tlbi vale2isnxs, x1 // encoding: [0xa1,0x93,0x0c,0xd5]
+// CHECK: tlbi vale3isnxs, x1 // encoding: [0xa1,0x93,0x0e,0xd5]
+// CHECK: tlbi vmalls12e1isnxs // encoding: [0xdf,0x93,0x0c,0xd5]
+// CHECK: tlbi vaale1isnxs, x1 // encoding: [0xe1,0x93,0x08,0xd5]
+// CHECK: tlbi ipas2e1nxs, x1 // encoding: [0x21,0x94,0x0c,0xd5]
+// CHECK: tlbi ipas2le1nxs, x1 // encoding: [0xa1,0x94,0x0c,0xd5]
+// CHECK: tlbi vmalle1nxs // encoding: [0x1f,0x97,0x08,0xd5]
+// CHECK: tlbi alle2nxs // encoding: [0x1f,0x97,0x0c,0xd5]
+// CHECK: tlbi alle3nxs // encoding: [0x1f,0x97,0x0e,0xd5]
+// CHECK: tlbi vae1nxs, x1 // encoding: [0x21,0x97,0x08,0xd5]
+// CHECK: tlbi vae2nxs, x1 // encoding: [0x21,0x97,0x0c,0xd5]
+// CHECK: tlbi vae3nxs, x1 // encoding: [0x21,0x97,0x0e,0xd5]
+// CHECK: tlbi aside1nxs, x1 // encoding: [0x41,0x97,0x08,0xd5]
+// CHECK: tlbi vaae1nxs, x1 // encoding: [0x61,0x97,0x08,0xd5]
+// CHECK: tlbi alle1nxs // encoding: [0x9f,0x97,0x0c,0xd5]
+// CHECK: tlbi vale1nxs, x1 // encoding: [0xa1,0x97,0x08,0xd5]
+// CHECK: tlbi vale2nxs, x1 // encoding: [0xa1,0x97,0x0c,0xd5]
+// CHECK: tlbi vale3nxs, x1 // encoding: [0xa1,0x97,0x0e,0xd5]
+// CHECK: tlbi vmalls12e1nxs // encoding: [0xdf,0x97,0x0c,0xd5]
+// CHECK: tlbi vaale1nxs, x1 // encoding: [0xe1,0x97,0x08,0xd5]
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE2ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE3ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE2ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE3ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ASIDE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAAE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE3ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAALE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE2nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE3nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE2nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE3nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ASIDE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAAE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE3nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAALE1nXS requires: xs
+
+ tlbi vmalle1osnxs
+ tlbi vae1osnxs, x1
+ tlbi aside1osnxs, x1
+ tlbi vaae1osnxs, x1
+ tlbi vale1osnxs, x1
+ tlbi vaale1osnxs, x1
+ tlbi ipas2e1osnxs, x1
+ tlbi ipas2le1osnxs, x1
+ tlbi vae2osnxs, x1
+ tlbi vale2osnxs, x1
+ tlbi vmalls12e1osnxs
+ tlbi vae3osnxs, x1
+ tlbi vale3osnxs, x1
+ tlbi alle2osnxs
+ tlbi alle1osnxs
+ tlbi alle3osnxs
+ tlbi rvae1nxs, x1
+ tlbi rvaae1nxs, x1
+ tlbi rvale1nxs, x1
+ tlbi rvaale1nxs, x1
+ tlbi rvae1isnxs, x1
+ tlbi rvaae1isnxs, x1
+ tlbi rvale1isnxs, x1
+ tlbi rvaale1isnxs, x1
+ tlbi rvae1osnxs, x1
+ tlbi rvaae1osnxs, x1
+ tlbi rvale1osnxs, x1
+ tlbi rvaale1osnxs, x1
+ tlbi ripas2e1isnxs, x1
+ tlbi ripas2le1isnxs, x1
+ tlbi ripas2e1nxs, x1
+ tlbi ripas2le1nxs, x1
+ tlbi ripas2e1osnxs, x1
+ tlbi ripas2le1osnxs, x1
+ tlbi rvae2nxs, x1
+ tlbi rvale2nxs, x1
+ tlbi rvae2isnxs, x1
+ tlbi rvale2isnxs, x1
+ tlbi rvae2osnxs, x1
+ tlbi rvale2osnxs, x1
+ tlbi rvae3nxs, x1
+ tlbi rvale3nxs, x1
+ tlbi rvae3isnxs, x1
+ tlbi rvale3isnxs, x1
+ tlbi rvae3osnxs, x1
+ tlbi rvale3osnxs, x1
+// CHECK: tlbi vmalle1osnxs // encoding: [0x1f,0x91,0x08,0xd5]
+// CHECK: tlbi vae1osnxs, x1 // encoding: [0x21,0x91,0x08,0xd5]
+// CHECK: tlbi aside1osnxs, x1 // encoding: [0x41,0x91,0x08,0xd5]
+// CHECK: tlbi vaae1osnxs, x1 // encoding: [0x61,0x91,0x08,0xd5]
+// CHECK: tlbi vale1osnxs, x1 // encoding: [0xa1,0x91,0x08,0xd5]
+// CHECK: tlbi vaale1osnxs, x1 // encoding: [0xe1,0x91,0x08,0xd5]
+// CHECK: tlbi ipas2e1osnxs, x1 // encoding: [0x01,0x94,0x0c,0xd5]
+// CHECK: tlbi ipas2le1osnxs, x1 // encoding: [0x81,0x94,0x0c,0xd5]
+// CHECK: tlbi vae2osnxs, x1 // encoding: [0x21,0x91,0x0c,0xd5]
+// CHECK: tlbi vale2osnxs, x1 // encoding: [0xa1,0x91,0x0c,0xd5]
+// CHECK: tlbi vmalls12e1osnxs // encoding: [0xdf,0x91,0x0c,0xd5]
+// CHECK: tlbi vae3osnxs, x1 // encoding: [0x21,0x91,0x0e,0xd5]
+// CHECK: tlbi vale3osnxs, x1 // encoding: [0xa1,0x91,0x0e,0xd5]
+// CHECK: tlbi alle2osnxs // encoding: [0x1f,0x91,0x0c,0xd5]
+// CHECK: tlbi alle1osnxs // encoding: [0x9f,0x91,0x0c,0xd5]
+// CHECK: tlbi alle3osnxs // encoding: [0x1f,0x91,0x0e,0xd5]
+// CHECK: tlbi rvae1nxs, x1 // encoding: [0x21,0x96,0x08,0xd5]
+// CHECK: tlbi rvaae1nxs, x1 // encoding: [0x61,0x96,0x08,0xd5]
+// CHECK: tlbi rvale1nxs, x1 // encoding: [0xa1,0x96,0x08,0xd5]
+// CHECK: tlbi rvaale1nxs, x1 // encoding: [0xe1,0x96,0x08,0xd5]
+// CHECK: tlbi rvae1isnxs, x1 // encoding: [0x21,0x92,0x08,0xd5]
+// CHECK: tlbi rvaae1isnxs, x1 // encoding: [0x61,0x92,0x08,0xd5]
+// CHECK: tlbi rvale1isnxs, x1 // encoding: [0xa1,0x92,0x08,0xd5]
+// CHECK: tlbi rvaale1isnxs, x1 // encoding: [0xe1,0x92,0x08,0xd5]
+// CHECK: tlbi rvae1osnxs, x1 // encoding: [0x21,0x95,0x08,0xd5]
+// CHECK: tlbi rvaae1osnxs, x1 // encoding: [0x61,0x95,0x08,0xd5]
+// CHECK: tlbi rvale1osnxs, x1 // encoding: [0xa1,0x95,0x08,0xd5]
+// CHECK: tlbi rvaale1osnxs, x1 // encoding: [0xe1,0x95,0x08,0xd5]
+// CHECK: tlbi ripas2e1isnxs, x1 // encoding: [0x41,0x90,0x0c,0xd5]
+// CHECK: tlbi ripas2le1isnxs, x1 // encoding: [0xc1,0x90,0x0c,0xd5]
+// CHECK: tlbi ripas2e1nxs, x1 // encoding: [0x41,0x94,0x0c,0xd5]
+// CHECK: tlbi ripas2le1nxs, x1 // encoding: [0xc1,0x94,0x0c,0xd5]
+// CHECK: tlbi ripas2e1osnxs, x1 // encoding: [0x61,0x94,0x0c,0xd5]
+// CHECK: tlbi ripas2le1osnxs, x1 // encoding: [0xe1,0x94,0x0c,0xd5]
+// CHECK: tlbi rvae2nxs, x1 // encoding: [0x21,0x96,0x0c,0xd5]
+// CHECK: tlbi rvale2nxs, x1 // encoding: [0xa1,0x96,0x0c,0xd5]
+// CHECK: tlbi rvae2isnxs, x1 // encoding: [0x21,0x92,0x0c,0xd5]
+// CHECK: tlbi rvale2isnxs, x1 // encoding: [0xa1,0x92,0x0c,0xd5]
+// CHECK: tlbi rvae2osnxs, x1 // encoding: [0x21,0x95,0x0c,0xd5]
+// CHECK: tlbi rvale2osnxs, x1 // encoding: [0xa1,0x95,0x0c,0xd5]
+// CHECK: tlbi rvae3nxs, x1 // encoding: [0x21,0x96,0x0e,0xd5]
+// CHECK: tlbi rvale3nxs, x1 // encoding: [0xa1,0x96,0x0e,0xd5]
+// CHECK: tlbi rvae3isnxs, x1 // encoding: [0x21,0x92,0x0e,0xd5]
+// CHECK: tlbi rvale3isnxs, x1 // encoding: [0xa1,0x92,0x0e,0xd5]
+// CHECK: tlbi rvae3osnxs, x1 // encoding: [0x21,0x95,0x0e,0xd5]
+// CHECK: tlbi rvale3osnxs, x1 // encoding: [0xa1,0x95,0x0e,0xd5]
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ASIDE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAAE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAALE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2E1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2LE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE2OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE2OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLS12E1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE3OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE3OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE2OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE3OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3nXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3ISnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3OSnXS requires: tlb-rmi, xs
diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
index 9114d30bc3d8..00242f471d0c 100644
--- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s
+++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
@@ -3334,16 +3334,16 @@
// CHECK-ERROR-NEXT: ^
dsb #-1
- dsb #16
+ dsb #17
dsb foo
dmb #-1
- dmb #16
+ dmb #17
dmb foo
// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}}
// CHECK-ERROR-NEXT: dsb #-1
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}}
-// CHECK-ERROR-NEXT: dsb #16
+// CHECK-ERROR-NEXT: dsb #17
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: invalid barrier option name
// CHECK-ERROR-NEXT: dsb foo
@@ -3352,7 +3352,7 @@
// CHECK-ERROR-NEXT: dmb #-1
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}}
-// CHECK-ERROR-NEXT: dmb #16
+// CHECK-ERROR-NEXT: dmb #17
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: invalid barrier option name
// CHECK-ERROR-NEXT: dmb foo
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
new file mode 100644
index 000000000000..9582131e6fdf
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
@@ -0,0 +1,11 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+hcx -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck --check-prefix=CHECK-NO-HCX %s
+
+[0x42,0x12,0x3c,0xd5]
+# CHECK: mrs x2, HCRX_EL2
+# CHECK-NO-HCX: mrs x2, S3_4_C1_C2_2
+
+[0x43,0x12,0x1c,0xd5]
+# CHECK: msr HCRX_EL2, x3
+# CHECK-NO-HCX: msr S3_4_C1_C2_2, x3
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
new file mode 100644
index 000000000000..232ba2dbcb52
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
@@ -0,0 +1,11 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+wfxt -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck --check-prefix=CHECK-NO-WFxT %s
+
+[0x11,0x10,0x03,0xd5]
+# CHECK: wfet x17
+# CHECK-NO-WFxT: msr S0_3_C1_C0_0, x17
+
+[0x23,0x10,0x03,0xd5]
+# CHECK: wfit x3
+# CHECK-NO-WFxT: msr S0_3_C1_C0_1, x3
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
new file mode 100644
index 000000000000..ce09954f5f0f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
@@ -0,0 +1,264 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.4a,+xs -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.4a -disassemble %s | FileCheck --check-prefix=CHECK-NO-XS %s
+
+[0x3f,0x32,0x03,0xd5]
+[0x3f,0x36,0x03,0xd5]
+[0x3f,0x3a,0x03,0xd5]
+[0x3f,0x3e,0x03,0xd5]
+# CHECK: dsb oshnxs
+# CHECK: dsb nshnxs
+# CHECK: dsb ishnxs
+# CHECK: dsb synxs
+# CHECK-NO-XS: msr S0_3_C3_C2_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C6_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C10_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C14_1, xzr
+
+[0x3f,0x30,0x03,0xd5]
+[0x3f,0x35,0x03,0xd5]
+[0x3f,0x3f,0x03,0xd5]
+# CHECK: msr S0_3_C3_C0_1, xzr
+# CHECK: msr S0_3_C3_C5_1, xzr
+# CHECK: msr S0_3_C3_C15_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C0_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C5_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C15_1, xzr
+
+[0x21,0x90,0x0c,0xd5]
+[0xa1,0x90,0x0c,0xd5]
+[0x1f,0x93,0x08,0xd5]
+[0x1f,0x93,0x0c,0xd5]
+[0x1f,0x93,0x0e,0xd5]
+[0x21,0x93,0x08,0xd5]
+[0x21,0x93,0x0c,0xd5]
+[0x21,0x93,0x0e,0xd5]
+[0x41,0x93,0x08,0xd5]
+[0x61,0x93,0x08,0xd5]
+[0x9f,0x93,0x0c,0xd5]
+[0xa1,0x93,0x08,0xd5]
+[0xa1,0x93,0x0c,0xd5]
+[0xa1,0x93,0x0e,0xd5]
+[0xdf,0x93,0x0c,0xd5]
+[0xe1,0x93,0x08,0xd5]
+[0x21,0x94,0x0c,0xd5]
+[0xa1,0x94,0x0c,0xd5]
+[0x1f,0x97,0x08,0xd5]
+[0x1f,0x97,0x0c,0xd5]
+[0x1f,0x97,0x0e,0xd5]
+[0x21,0x97,0x08,0xd5]
+[0x21,0x97,0x0c,0xd5]
+[0x21,0x97,0x0e,0xd5]
+[0x41,0x97,0x08,0xd5]
+[0x61,0x97,0x08,0xd5]
+[0x9f,0x97,0x0c,0xd5]
+[0xa1,0x97,0x08,0xd5]
+[0xa1,0x97,0x0c,0xd5]
+[0xa1,0x97,0x0e,0xd5]
+[0xdf,0x97,0x0c,0xd5]
+[0xe1,0x97,0x08,0xd5]
+# CHECK: tlbi ipas2e1isnxs, x1
+# CHECK: tlbi ipas2le1isnxs, x1
+# CHECK: tlbi vmalle1isnxs
+# CHECK: tlbi alle2isnxs
+# CHECK: tlbi alle3isnxs
+# CHECK: tlbi vae1isnxs, x1
+# CHECK: tlbi vae2isnxs, x1
+# CHECK: tlbi vae3isnxs, x1
+# CHECK: tlbi aside1isnxs, x1
+# CHECK: tlbi vaae1isnxs, x1
+# CHECK: tlbi alle1isnxs
+# CHECK: tlbi vale1isnxs, x1
+# CHECK: tlbi vale2isnxs, x1
+# CHECK: tlbi vale3isnxs, x1
+# CHECK: tlbi vmalls12e1isnxs
+# CHECK: tlbi vaale1isnxs, x1
+# CHECK: tlbi ipas2e1nxs, x1
+# CHECK: tlbi ipas2le1nxs, x1
+# CHECK: tlbi vmalle1nxs
+# CHECK: tlbi alle2nxs
+# CHECK: tlbi alle3nxs
+# CHECK: tlbi vae1nxs, x1
+# CHECK: tlbi vae2nxs, x1
+# CHECK: tlbi vae3nxs, x1
+# CHECK: tlbi aside1nxs, x1
+# CHECK: tlbi vaae1nxs, x1
+# CHECK: tlbi alle1nxs
+# CHECK: tlbi vale1nxs, x1
+# CHECK: tlbi vale2nxs, x1
+# CHECK: tlbi vale3nxs, x1
+# CHECK: tlbi vmalls12e1nxs
+# CHECK: tlbi vaale1nxs, x1
+# CHECK_NO_XS: sys #4, c9, c0, #1, x1
+# CHECK_NO_XS: sys #4, c9, c0, #5, x1
+# CHECK_NO_XS: sys #0, c9, c3, #0
+# CHECK_NO_XS: sys #4, c9, c3, #0
+# CHECK_NO_XS: sys #6, c9, c3, #0
+# CHECK_NO_XS: sys #0, c9, c3, #1, x1
+# CHECK_NO_XS: sys #4, c9, c3, #1, x1
+# CHECK_NO_XS: sys #6, c9, c3, #1, x1
+# CHECK_NO_XS: sys #0, c9, c3, #2, x1
+# CHECK_NO_XS: sys #0, c9, c3, #3, x1
+# CHECK_NO_XS: sys #4, c9, c3, #4
+# CHECK_NO_XS: sys #0, c9, c3, #5, x1
+# CHECK_NO_XS: sys #4, c9, c3, #5, x1
+# CHECK_NO_XS: sys #6, c9, c3, #5, x1
+# CHECK_NO_XS: sys #4, c9, c3, #6
+# CHECK_NO_XS: sys #0, c9, c3, #7, x1
+# CHECK_NO_XS: sys #4, c9, c4, #1, x1
+# CHECK_NO_XS: sys #4, c9, c4, #5, x1
+# CHECK_NO_XS: sys #0, c9, c7, #0
+# CHECK_NO_XS: sys #4, c9, c7, #0
+# CHECK_NO_XS: sys #6, c9, c7, #0
+# CHECK_NO_XS: sys #0, c9, c7, #1, x1
+# CHECK_NO_XS: sys #4, c9, c7, #1, x1
+# CHECK_NO_XS: sys #6, c9, c7, #1, x1
+# CHECK_NO_XS: sys #0, c9, c7, #2, x1
+# CHECK_NO_XS: sys #0, c9, c7, #3, x1
+# CHECK_NO_XS: sys #4, c9, c7, #4
+# CHECK_NO_XS: sys #0, c9, c7, #5, x1
+# CHECK_NO_XS: sys #4, c9, c7, #5, x1
+# CHECK_NO_XS: sys #6, c9, c7, #5, x1
+# CHECK_NO_XS: sys #4, c9, c7, #6
+# CHECK_NO_XS: sys #0, c9, c7, #7, x1
+
+[0x1f,0x91,0x08,0xd5]
+[0x21,0x91,0x08,0xd5]
+[0x41,0x91,0x08,0xd5]
+[0x61,0x91,0x08,0xd5]
+[0xa1,0x91,0x08,0xd5]
+[0xe1,0x91,0x08,0xd5]
+[0x01,0x94,0x0c,0xd5]
+[0x81,0x94,0x0c,0xd5]
+[0x21,0x91,0x0c,0xd5]
+[0xa1,0x91,0x0c,0xd5]
+[0xdf,0x91,0x0c,0xd5]
+[0x21,0x91,0x0e,0xd5]
+[0xa1,0x91,0x0e,0xd5]
+[0x1f,0x91,0x0c,0xd5]
+[0x9f,0x91,0x0c,0xd5]
+[0x1f,0x91,0x0e,0xd5]
+[0x21,0x96,0x08,0xd5]
+[0x61,0x96,0x08,0xd5]
+[0xa1,0x96,0x08,0xd5]
+[0xe1,0x96,0x08,0xd5]
+[0x21,0x92,0x08,0xd5]
+[0x61,0x92,0x08,0xd5]
+[0xa1,0x92,0x08,0xd5]
+[0xe1,0x92,0x08,0xd5]
+[0x21,0x95,0x08,0xd5]
+[0x61,0x95,0x08,0xd5]
+[0xa1,0x95,0x08,0xd5]
+[0xe1,0x95,0x08,0xd5]
+[0x41,0x90,0x0c,0xd5]
+[0xc1,0x90,0x0c,0xd5]
+[0x41,0x94,0x0c,0xd5]
+[0xc1,0x94,0x0c,0xd5]
+[0x61,0x94,0x0c,0xd5]
+[0xe1,0x94,0x0c,0xd5]
+[0x21,0x96,0x0c,0xd5]
+[0xa1,0x96,0x0c,0xd5]
+[0x21,0x92,0x0c,0xd5]
+[0xa1,0x92,0x0c,0xd5]
+[0x21,0x95,0x0c,0xd5]
+[0xa1,0x95,0x0c,0xd5]
+[0x21,0x96,0x0e,0xd5]
+[0xa1,0x96,0x0e,0xd5]
+[0x21,0x92,0x0e,0xd5]
+[0xa1,0x92,0x0e,0xd5]
+[0x21,0x95,0x0e,0xd5]
+[0xa1,0x95,0x0e,0xd5]
+# CHECK: tlbi vmalle1osnxs
+# CHECK: tlbi vae1osnxs, x1
+# CHECK: tlbi aside1osnxs, x1
+# CHECK: tlbi vaae1osnxs, x1
+# CHECK: tlbi vale1osnxs, x1
+# CHECK: tlbi vaale1osnxs, x1
+# CHECK: tlbi ipas2e1osnxs, x1
+# CHECK: tlbi ipas2le1osnxs, x1
+# CHECK: tlbi vae2osnxs, x1
+# CHECK: tlbi vale2osnxs, x1
+# CHECK: tlbi vmalls12e1osnxs
+# CHECK: tlbi vae3osnxs, x1
+# CHECK: tlbi vale3osnxs, x1
+# CHECK: tlbi alle2osnxs
+# CHECK: tlbi alle1osnxs
+# CHECK: tlbi alle3osnxs
+# CHECK: tlbi rvae1nxs, x1
+# CHECK: tlbi rvaae1nxs, x1
+# CHECK: tlbi rvale1nxs, x1
+# CHECK: tlbi rvaale1nxs, x1
+# CHECK: tlbi rvae1isnxs, x1
+# CHECK: tlbi rvaae1isnxs, x1
+# CHECK: tlbi rvale1isnxs, x1
+# CHECK: tlbi rvaale1isnxs, x1
+# CHECK: tlbi rvae1osnxs, x1
+# CHECK: tlbi rvaae1osnxs, x1
+# CHECK: tlbi rvale1osnxs, x1
+# CHECK: tlbi rvaale1osnxs, x1
+# CHECK: tlbi ripas2e1isnxs, x1
+# CHECK: tlbi ripas2le1isnxs, x1
+# CHECK: tlbi ripas2e1nxs, x1
+# CHECK: tlbi ripas2le1nxs, x1
+# CHECK: tlbi ripas2e1osnxs, x1
+# CHECK: tlbi ripas2le1osnxs, x1
+# CHECK: tlbi rvae2nxs, x1
+# CHECK: tlbi rvale2nxs, x1
+# CHECK: tlbi rvae2isnxs, x1
+# CHECK: tlbi rvale2isnxs, x1
+# CHECK: tlbi rvae2osnxs, x1
+# CHECK: tlbi rvale2osnxs, x1
+# CHECK: tlbi rvae3nxs, x1
+# CHECK: tlbi rvale3nxs, x1
+# CHECK: tlbi rvae3isnxs, x1
+# CHECK: tlbi rvale3isnxs, x1
+# CHECK: tlbi rvae3osnxs, x1
+# CHECK: tlbi rvale3osnxs, x1
+# CHECK_NO_XS: sys #0, c9, c1, #0
+# CHECK_NO_XS: sys #0, c9, c1, #1, x1
+# CHECK_NO_XS: sys #0, c9, c1, #2, x1
+# CHECK_NO_XS: sys #0, c9, c1, #3, x1
+# CHECK_NO_XS: sys #0, c9, c1, #5, x1
+# CHECK_NO_XS: sys #0, c9, c1, #7, x1
+# CHECK_NO_XS: sys #4, c9, c4, #0, x1
+# CHECK_NO_XS: sys #4, c9, c4, #4, x1
+# CHECK_NO_XS: sys #4, c9, c1, #1, x1
+# CHECK_NO_XS: sys #4, c9, c1, #5, x1
+# CHECK_NO_XS: sys #4, c9, c1, #6
+# CHECK_NO_XS: sys #6, c9, c1, #1, x1
+# CHECK_NO_XS: sys #6, c9, c1, #5, x1
+# CHECK_NO_XS: sys #4, c9, c1, #0
+# CHECK_NO_XS: sys #4, c9, c1, #4
+# CHECK_NO_XS: sys #6, c9, c1, #0
+# CHECK_NO_XS: sys #0, c9, c6, #1, x1
+# CHECK_NO_XS: sys #0, c9, c6, #3, x1
+# CHECK_NO_XS: sys #0, c9, c6, #5, x1
+# CHECK_NO_XS: sys #0, c9, c6, #7, x1
+# CHECK_NO_XS: sys #0, c9, c2, #1, x1
+# CHECK_NO_XS: sys #0, c9, c2, #3, x1
+# CHECK_NO_XS: sys #0, c9, c2, #5, x1
+# CHECK_NO_XS: sys #0, c9, c2, #7, x1
+# CHECK_NO_XS: sys #0, c9, c5, #1, x1
+# CHECK_NO_XS: sys #0, c9, c5, #3, x1
+# CHECK_NO_XS: sys #0, c9, c5, #5, x1
+# CHECK_NO_XS: sys #0, c9, c5, #7, x1
+# CHECK_NO_XS: sys #4, c9, c0, #2, x1
+# CHECK_NO_XS: sys #4, c9, c0, #6, x1
+# CHECK_NO_XS: sys #4, c9, c4, #2, x1
+# CHECK_NO_XS: sys #4, c9, c4, #6, x1
+# CHECK_NO_XS: sys #4, c9, c4, #3, x1
+# CHECK_NO_XS: sys #4, c9, c4, #7, x1
+# CHECK_NO_XS: sys #4, c9, c6, #1, x1
+# CHECK_NO_XS: sys #4, c9, c6, #5, x1
+# CHECK_NO_XS: sys #4, c9, c2, #1, x1
+# CHECK_NO_XS: sys #4, c9, c2, #5, x1
+# CHECK_NO_XS: sys #4, c9, c5, #1, x1
+# CHECK_NO_XS: sys #4, c9, c5, #5, x1
+# CHECK_NO_XS: sys #6, c9, c6, #1, x1
+# CHECK_NO_XS: sys #6, c9, c6, #5, x1
+# CHECK_NO_XS: sys #6, c9, c2, #1, x1
+# CHECK_NO_XS: sys #6, c9, c2, #5, x1
+# CHECK_NO_XS: sys #6, c9, c5, #1, x1
+# CHECK_NO_XS: sys #6, c9, c5, #5, x1
+# CHECK_NO_XS: sys #0, c9, c1, #0
+# CHECK_NO_XS: sys #4, c9, c0, #1, x1
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 922b428921ad..a086f66a0b01 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3533,6 +3533,7 @@
# CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}
# CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}
# CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}
+# CHECK: mrs x9, {{id_aa64isar2_el1|ID_AA64ISAR2_EL1}}
# CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}
# CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}
# CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}}
@@ -4090,6 +4091,7 @@
0xa9 0x5 0x38 0xd5
0x9 0x6 0x38 0xd5
0x29 0x6 0x38 0xd5
+0x49 0x06 0x38 0xd5
0x9 0x7 0x38 0xd5
0x29 0x7 0x38 0xd5
0x9 0x10 0x38 0xd5
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