[llvm-branch-commits] [llvm] eb66bf0 - [AMDGPU] Print SCRATCH_EN field after the kernel

[Stanislav Mekhanoshin via llvm-branch-commits]

Author: Stanislav Mekhanoshin
Date: 2020-12-15T22:44:30-08:00
New Revision: eb66bf0802f96458b24a9c6eb9bd6451d8f90110

URL: https://github.com/llvm/llvm-project/commit/eb66bf0802f96458b24a9c6eb9bd6451d8f90110
DIFF: https://github.com/llvm/llvm-project/commit/eb66bf0802f96458b24a9c6eb9bd6451d8f90110.diff

LOG: [AMDGPU] Print SCRATCH_EN field after the kernel

Differential Revision: https://reviews.llvm.org/D93353

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index a14f846b76d1..7ca049280744 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -538,6 +538,9 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
     OutStreamer->emitRawComment(
       " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
 
+    OutStreamer->emitRawComment(
+      " COMPUTE_PGM_RSRC2:SCRATCH_EN: " +
+      Twine(G_00B84C_SCRATCH_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
     OutStreamer->emitRawComment(
       " COMPUTE_PGM_RSRC2:USER_SGPR: " +
       Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
index 39029e359889..455c19fcdfc2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
@@ -3,7 +3,14 @@
 ; Make sure flat_scratch_init is set
 
 ; GCN-LABEL: {{^}}stack_object_addrspacecast_in_kernel_no_calls:
-; GCN: .amdhsa_user_sgpr_flat_scratch_init 1
+; GCN:     s_add_u32 flat_scratch_lo, s4, s7
+; GCN:     s_addc_u32 flat_scratch_hi, s5, 0
+; GCN:     flat_store_dword
+; GCN:     .amdhsa_user_sgpr_flat_scratch_init 1
+; GCN:     .amdhsa_system_sgpr_private_segment_wavefront_offset
+; GCN-NOT: .amdhsa_reserve_flat_scratch
+; GCN:     COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
+; GCN:     COMPUTE_PGM_RSRC2:USER_SGPR: 6
 define amdgpu_kernel void @stack_object_addrspacecast_in_kernel_no_calls() {
   %alloca = alloca i32, addrspace(5)
   %cast = addrspacecast i32 addrspace(5)* %alloca to i32*
@@ -13,7 +20,15 @@ define amdgpu_kernel void @stack_object_addrspacecast_in_kernel_no_calls() {
 
 ; TODO: Could optimize out in this case
 ; GCN-LABEL: {{^}}stack_object_in_kernel_no_calls:
-; GCN: .amdhsa_user_sgpr_flat_scratch_init 1
+; GCN:     s_add_u32 flat_scratch_lo, s4, s7
+; GCN:     s_addc_u32 flat_scratch_hi, s5, 0
+; GCN:     buffer_store_dword
+; GCN:     .amdhsa_user_sgpr_private_segment_buffer 1
+; GCN:     .amdhsa_user_sgpr_flat_scratch_init 1
+; GCN:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
+; GCN-NOT: .amdhsa_reserve_flat_scratch
+; GCN:     COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
+; GCN:     COMPUTE_PGM_RSRC2:USER_SGPR: 6
 define amdgpu_kernel void @stack_object_in_kernel_no_calls() {
   %alloca = alloca i32, addrspace(5)
   store volatile i32 0, i32 addrspace(5)* %alloca
@@ -21,7 +36,13 @@ define amdgpu_kernel void @stack_object_in_kernel_no_calls() {
 }
 
 ; GCN-LABEL: {{^}}kernel_no_calls_no_stack:
-; GCN: .amdhsa_user_sgpr_flat_scratch_init 0
+; GCN-NOT: flat_scratch
+; GCN:     .amdhsa_user_sgpr_private_segment_buffer 1
+; GCN:     .amdhsa_user_sgpr_flat_scratch_init 0
+; GCN:     .amdhsa_system_sgpr_private_segment_wavefront_offset 0
+; GCN:     .amdhsa_reserve_flat_scratch 0
+; GCN:     COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
+; GCN:     COMPUTE_PGM_RSRC2:USER_SGPR: 4
 define amdgpu_kernel void @kernel_no_calls_no_stack() {
   ret void
 }