[llvm-branch-commits] [llvm] 1638564 - [Hexagon] Emit enough stores when aligning vector addresses

[Krzysztof Parzyszek via llvm-branch-commits]

Author: Krzysztof Parzyszek
Date: 2020-12-15T18:59:53-06:00
New Revision: 16385643bbf20396eb8fdef40388fb97a47c2f9d

URL: https://github.com/llvm/llvm-project/commit/16385643bbf20396eb8fdef40388fb97a47c2f9d
DIFF: https://github.com/llvm/llvm-project/commit/16385643bbf20396eb8fdef40388fb97a47c2f9d.diff

LOG: [Hexagon] Emit enough stores when aligning vector addresses

Added: 
    llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 2d90e37349e5..aa8236d6d54f 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -820,7 +820,9 @@ auto AlignVectors::realignGroup(const MoveGroup &Move) const -> bool {
       return Builder.CreateBitCast(Val, VecTy);
     };
 
-    for (int i = -1; i != NumSectors; ++i) {
+    // Create an extra "undef" sector at the beginning and at the end.
+    // They will be used as the left/right filler in the vlalign step.
+    for (int i = -1; i != NumSectors + 1; ++i) {
       ByteSpan Section = VSpan.section(i * ScLen, ScLen).normalize();
       Value *AccumV = UndefValue::get(SecTy);
       Value *AccumM = HVC.getNullValue(SecTy);
@@ -838,14 +840,14 @@ auto AlignVectors::realignGroup(const MoveGroup &Move) const -> bool {
     }
 
     // vlalign
-    for (int j = 1; j != NumSectors + 1; ++j) {
+    for (int j = 1; j != NumSectors + 2; ++j) {
       ASpanV[j - 1].Seg.Val = HVC.vlalignb(Builder, ASpanV[j - 1].Seg.Val,
                                            ASpanV[j].Seg.Val, AlignVal);
       ASpanM[j - 1].Seg.Val = HVC.vlalignb(Builder, ASpanM[j - 1].Seg.Val,
                                            ASpanM[j].Seg.Val, AlignVal);
     }
 
-    for (int i = 0; i != NumSectors; ++i) {
+    for (int i = 0; i != NumSectors + 1; ++i) {
       Value *Ptr = createAdjustedPointer(Builder, AlignAddr, SecTy, i * ScLen);
       Value *Val = ASpanV[i].Seg.Val;
       Value *Mask = ASpanM[i].Seg.Val; // bytes

diff  --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll
new file mode 100644
index 000000000000..ddf35fb40608
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Make sure we generate 3 aligned stores.
+; CHECK: vmem({{.*}}) =
+; CHECK: vmem({{.*}}) =
+; CHECK: vmem({{.*}}) =
+; CHECK-NOT: vmem
+
+define void @f0(i16* %a0, i32 %a11, <64 x i16> %a22, <64 x i16> %a3) #0 {
+b0:
+  %v0 = add i32 %a11, 64
+  %v1 = getelementptr i16, i16* %a0, i32 %v0
+  %v2 = bitcast i16* %v1 to <64 x i16>*
+  store <64 x i16> %a22, <64 x i16>* %v2, align 2
+  %v33 = add i32 %a11, 128
+  %v44 = getelementptr i16, i16* %a0, i32 %v33
+  %v5 = bitcast i16* %v44 to <64 x i16>*
+  store <64 x i16> %a3, <64 x i16>* %v5, align 2
+  ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b" }