[llvm-branch-commits] [llvm] 71601d2 - [Hexagon] Fix bitcasting v1i8 -> i8

[Krzysztof Parzyszek via llvm-branch-commits]

Author: Krzysztof Parzyszek
Date: 2020-12-15T16:01:24-06:00
New Revision: 71601d2ac9954cb59c443cb3ae442cb106df35d4

URL: https://github.com/llvm/llvm-project/commit/71601d2ac9954cb59c443cb3ae442cb106df35d4
DIFF: https://github.com/llvm/llvm-project/commit/71601d2ac9954cb59c443cb3ae442cb106df35d4.diff

LOG: [Hexagon] Fix bitcasting v1i8 -> i8

Added: 
    llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index b60758a8be8a..c8994a3a28a3 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3151,10 +3151,12 @@ HexagonTargetLowering::ReplaceNodeResults(SDNode *N,
     case ISD::BITCAST:
       // Handle a bitcast from v8i1 to i8.
       if (N->getValueType(0) == MVT::i8) {
-        SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
-                             N->getOperand(0), DAG);
-        SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
-        Results.push_back(T);
+        if (N->getOperand(0).getValueType() == MVT::v8i1) {
+          SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
+                               N->getOperand(0), DAG);
+          SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
+          Results.push_back(T);
+        }
       }
       break;
   }

diff  --git a/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll b/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll
new file mode 100644
index 000000000000..77696a331a8f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon  < %s | FileCheck %s
+
+; This shouldn't crash.
+
+define i8 @fred(<4 x i8>* %a0) #0 {
+; CHECK-LABEL: fred:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = memw(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = extractu(r0,#8,#16)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = load <4 x i8>, <4 x i8>* %a0, align 4
+  %v1 = shufflevector <4 x i8> %v0, <4 x i8> undef, <1 x i32> <i32 2>
+  %v2 = bitcast <1 x i8> %v1 to i8
+  ret i8 %v2
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv66" }