[llvm-branch-commits] [llvm] b0e5aea - [X86] Remove unnecessary SUBV_BROADCAST combines. NFCI.

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2020-12-15T16:54:34Z
New Revision: b0e5aea5572bbfaef1ad47777a7089b2879d2df4

URL: https://github.com/llvm/llvm-project/commit/b0e5aea5572bbfaef1ad47777a7089b2879d2df4
DIFF: https://github.com/llvm/llvm-project/commit/b0e5aea5572bbfaef1ad47777a7089b2879d2df4.diff

LOG: [X86] Remove unnecessary SUBV_BROADCAST combines. NFCI.

Noticed while dealing with D92645 - these are now handled by getFauxShuffleMask + shuffle combining code.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bd904327f8e7..bd106f336098 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35172,23 +35172,6 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
     return CanonicalizeShuffleInput(RootVT, V1);
   }
 
-  // Attempt to match a subvector broadcast.
-  // shuffle(insert_subvector(undef, sub, 0), undef, 0, 0, 0, 0)
-  if (UnaryShuffle &&
-      (BaseMaskEltSizeInBits == 128 || BaseMaskEltSizeInBits == 256)) {
-    if (isUndefOrEqual(BaseMask, 0)) {
-      SDValue Src = Inputs[0];
-      if (Src.getOpcode() == ISD::INSERT_SUBVECTOR &&
-          Src.getOperand(0).isUndef() &&
-          Src.getOperand(1).getValueSizeInBits() == BaseMaskEltSizeInBits &&
-          MayFoldLoad(Src.getOperand(1)) && isNullConstant(Src.getOperand(2))) {
-        return DAG.getBitcast(RootVT, DAG.getNode(X86ISD::SUBV_BROADCAST, DL,
-                                                  Src.getValueType(),
-                                                  Src.getOperand(1)));
-      }
-    }
-  }
-
   // Handle 128/256-bit lane shuffles of 512-bit vectors.
   if (RootVT.is512BitVector() &&
       (NumBaseMaskElts == 2 || NumBaseMaskElts == 4)) {
@@ -48846,10 +48829,8 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
 
   // Repeated subvectors.
   if (IsSplat) {
-    // If this broadcast/subv_broadcast is inserted into both halves, use a
-    // larger broadcast/subv_broadcast.
-    if (Op0.getOpcode() == X86ISD::VBROADCAST ||
-        Op0.getOpcode() == X86ISD::SUBV_BROADCAST)
+    // If this broadcast is inserted into both halves, use a larger broadcast.
+    if (Op0.getOpcode() == X86ISD::VBROADCAST)
       return DAG.getNode(Op0.getOpcode(), DL, VT, Op0.getOperand(0));
 
     // If this broadcast_load is inserted into both halves, use a larger