[llvm-branch-commits] [llvm] ebef921 - [SystemZ] Remove most hard-coded R1D instances for sibcalls
Ulrich Weigand via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Dec 15 07:36:28 PST 2020
Author: Ulrich Weigand
Date: 2020-12-15T16:31:18+01:00
New Revision: ebef92169ca5a50fb8aeec08f35ccb919311acc1
URL: https://github.com/llvm/llvm-project/commit/ebef92169ca5a50fb8aeec08f35ccb919311acc1
DIFF: https://github.com/llvm/llvm-project/commit/ebef92169ca5a50fb8aeec08f35ccb919311acc1.diff
LOG: [SystemZ] Remove most hard-coded R1D instances for sibcalls
Indirect sibling calls need to use %r1 to hold the target address.
This is currently hard-coded in many places. This is not only
unnecessary, but makes future changes in this area difficult.
This patch now encodes the target address as operand without
hard coding a register in most places throughout the MI back-end.
Code generation still always uses %r1, but this is now decided
solely in one place in SystemZTargetLowering::LowerCall.
NFC intended.
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
index 4109bfc11337..584737e1d940 100644
--- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -236,14 +236,15 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
break;
case SystemZ::CallBR:
- LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
+ LoweredMI = MCInstBuilder(SystemZ::BR)
+ .addReg(MI->getOperand(0).getReg());
break;
case SystemZ::CallBCR:
LoweredMI = MCInstBuilder(SystemZ::BCR)
.addImm(MI->getOperand(0).getImm())
.addImm(MI->getOperand(1).getImm())
- .addReg(SystemZ::R1D);
+ .addReg(MI->getOperand(2).getReg());
break;
case SystemZ::CRBCall:
@@ -251,7 +252,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
@@ -260,7 +261,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
@@ -269,7 +270,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(MI->getOperand(0).getReg())
.addImm(MI->getOperand(1).getImm())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
@@ -278,7 +279,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(MI->getOperand(0).getReg())
.addImm(MI->getOperand(1).getImm())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
@@ -287,7 +288,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
@@ -296,7 +297,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
@@ -305,7 +306,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(MI->getOperand(0).getReg())
.addImm(MI->getOperand(1).getImm())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
@@ -314,7 +315,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(MI->getOperand(0).getReg())
.addImm(MI->getOperand(1).getImm())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
index 2f0cf0317029..19b703bbb226 100644
--- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
@@ -640,18 +640,22 @@ bool SystemZElimCompare::fuseCompareOperations(
MachineOperand CCMask(MBBI->getOperand(1));
assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
"Invalid condition-code mask for integer comparison");
- // This is only valid for CompareAndBranch.
+ // This is only valid for CompareAndBranch and CompareAndSibcall.
MachineOperand Target(MBBI->getOperand(
- Type == SystemZII::CompareAndBranch ? 2 : 0));
+ (Type == SystemZII::CompareAndBranch ||
+ Type == SystemZII::CompareAndSibcall) ? 2 : 0));
const uint32_t *RegMask;
if (Type == SystemZII::CompareAndSibcall)
- RegMask = MBBI->getOperand(2).getRegMask();
+ RegMask = MBBI->getOperand(3).getRegMask();
// Clear out all current operands.
int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
assert(CCUse >= 0 && "BRC/BCR must use CC");
Branch->RemoveOperand(CCUse);
- // Remove target (branch) or regmask (sibcall).
+ // Remove regmask (sibcall).
+ if (Type == SystemZII::CompareAndSibcall)
+ Branch->RemoveOperand(3);
+ // Remove target (branch or sibcall).
if (Type == SystemZII::CompareAndBranch ||
Type == SystemZII::CompareAndSibcall)
Branch->RemoveOperand(2);
@@ -678,8 +682,10 @@ bool SystemZElimCompare::fuseCompareOperations(
RegState::ImplicitDefine | RegState::Dead);
}
- if (Type == SystemZII::CompareAndSibcall)
+ if (Type == SystemZII::CompareAndSibcall) {
+ MIB.add(Target);
MIB.addRegMask(RegMask);
+ }
// Clear any intervening kills of SrcReg and SrcReg2.
MBBI = Compare;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index c51cf61cc4dd..bf01c262afe1 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -752,11 +752,14 @@ bool SystemZInstrInfo::PredicateInstruction(
return true;
}
if (Opcode == SystemZ::CallBR) {
- const uint32_t *RegMask = MI.getOperand(0).getRegMask();
+ MachineOperand Target = MI.getOperand(0);
+ const uint32_t *RegMask = MI.getOperand(1).getRegMask();
+ MI.RemoveOperand(1);
MI.RemoveOperand(0);
MI.setDesc(get(SystemZ::CallBCR));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(CCValid).addImm(CCMask)
+ .add(Target)
.addRegMask(RegMask)
.addReg(SystemZ::CC, RegState::Implicit);
return true;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index c37e30556ddb..6e4f9e7f4922 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -290,33 +290,32 @@ let isCall = 1, Defs = [R14D, CC] in {
[(z_tls_ldcall tglobaltlsaddr:$I2)]>;
}
-// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards
-// are argument registers and since branching to R0 is a no-op.
+// Sibling calls.
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
[(z_sibcall pcrel32:$I2)]>;
- let Uses = [R1D] in
- def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
+ def CallBR : Alias<2, (outs), (ins ADDR64:$R2),
+ [(z_sibcall ADDR64:$R2)]>;
}
// Conditional sibling calls.
let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in {
def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,
pcrel32:$I2), []>;
- let Uses = [R1D] in
- def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
+ def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1,
+ ADDR64:$R2), []>;
}
// Fused compare and conditional sibling calls.
-let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in {
- def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
- def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
- def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
- def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
- def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
- def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
- def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
- def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
+let isCall = 1, isTerminator = 1, isReturn = 1 in {
+ def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;
+ def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;
+ def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>;
+ def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>;
+ def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;
+ def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;
+ def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>;
+ def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>;
}
// A return instruction (br %r14).
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