[llvm-branch-commits] [llvm] 1de3e7f - [ARM] Improve handling of empty VPT blocks in tail predicated loops
David Green via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Dec 14 03:21:24 PST 2020
Author: David Green
Date: 2020-12-14T11:17:01Z
New Revision: 1de3e7fd620bc9db2df96a12401bde4bde722785
URL: https://github.com/llvm/llvm-project/commit/1de3e7fd620bc9db2df96a12401bde4bde722785
DIFF: https://github.com/llvm/llvm-project/commit/1de3e7fd620bc9db2df96a12401bde4bde722785.diff
LOG: [ARM] Improve handling of empty VPT blocks in tail predicated loops
A vpt block that just contains either VPST;VCTP or VPT;VCTP, once the
VCTP is removed will become invalid. This fixed the first by removing
the now empty block and bails out for the second, as we have no simple
way of converting a VPT to a VCMP.
Differential Revision: https://reviews.llvm.org/D92369
Added:
Modified:
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 52ca722a2e0c..2b53f57a7f09 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -312,6 +312,14 @@ namespace {
continue;
SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
+ // We don't know how to convert a block with just a VPT;VCTP into
+ // anything valid once we remove the VCTP. For now just bail out.
+ assert(isVPTOpcode(Insts.front()->getOpcode()) &&
+ "Expected VPT block to start with a VPST or VPT!");
+ if (Insts.size() == 2 && Insts.front()->getOpcode() != ARM::MVE_VPST &&
+ isVCTP(Insts.back()))
+ return false;
+
for (auto *MI : Insts) {
// Check that any internal VCTPs are 'Then' predicated.
if (isVCTP(MI) && getVPTInstrPredicate(*MI) != ARMVCC::Then)
@@ -1547,9 +1555,15 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
LoLoop.ToRemove.insert(VPST);
} else if (Block.containsVCTP()) {
- // The vctp will be removed, so the block mask of the vp(s)t will need
- // to be recomputed.
- LoLoop.BlockMasksToRecompute.insert(Insts.front());
+ // The vctp will be removed, so either the entire block will be dead or
+ // the block mask of the vp(s)t will need to be recomputed.
+ MachineInstr *VPST = Insts.front();
+ if (Block.size() == 2) {
+ assert(VPST->getOpcode() == ARM::MVE_VPST &&
+ "Found a VPST in an otherwise empty vpt block");
+ LoLoop.ToRemove.insert(VPST);
+ } else
+ LoLoop.BlockMasksToRecompute.insert(VPST);
} else if (Insts.front()->getOpcode() == ARM::MVE_VPST) {
// If this block starts with a VPST then attempt to merge it with the
// preceeding un-merged VCMP into a VPT. This VCMP comes from a VPT
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
index f7e1d86fd1b0..ab6d05ca6aac 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
@@ -149,6 +149,16 @@
unreachable
}
+ define arm_aapcs_vfpcc void @emptyblock() {
+ unreachable
+ }
+ define arm_aapcs_vfpcc void @predvcmp() {
+ unreachable
+ }
+ define arm_aapcs_vfpcc void @predvpt() {
+ unreachable
+ }
+
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
declare i32 @llvm.start.loop.iterations.i32(i32)
@@ -835,7 +845,7 @@ body: |
; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r2, $r3
- ; CHECK: MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 8, implicit-def $vpr
+ ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr
; CHECK: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup:
@@ -868,7 +878,7 @@ body: |
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3
- MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 8, implicit-def $vpr
+ MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr
renamable $vpr = MVE_VCMPs32r killed renamable $q0, renamable $r3, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
@@ -1001,3 +1011,308 @@ body: |
bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
...
+---
+name: emptyblock
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body: |
+ ; CHECK-LABEL: name: emptyblock
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x50000000), %bb.3(0x30000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 12
+ ; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr
+ ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ ; CHECK: renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg
+ ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r0
+ ; CHECK: bb.2 (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r1
+ ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
+ ; CHECK: MVE_VPST 8, implicit $vpr
+ ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store 16, align 4)
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK: bb.3:
+ ; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0
+ bb.0:
+ successors: %bb.1(0x50000000), %bb.3(0x30000000)
+ liveins: $r0, $r1, $r2, $r7, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_offset 12
+ tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr
+ renamable $r3, dead $cpsr = tADDi3 renamable $r0, 3, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+ renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg
+ $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg
+ VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
+ renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r0
+
+ bb.2 (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $r0, $r1
+
+ renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
+ MVE_VPST 8, implicit $vpr
+ renamable $vpr = MVE_VCTP32 renamable $r0, 1, killed renamable $vpr
+ renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
+ MVE_VPST 8, implicit $vpr
+ renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store 16, align 4)
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3:
+ $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0
+...
+---
+name: predvcmp
+alignment: 8
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+ - id: 0
+ value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
+ alignment: 8
+ isTargetSpecific: false
+body: |
+ ; CHECK-LABEL: name: predvcmp
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 11, 8, implicit-def $itstate
+ ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
+ ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load 16 from constant-pool, align 8)
+ ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
+ ; CHECK: bb.2 (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1
+ ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
+ ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16, align 4)
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK: bb.3:
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+ ; CHECK: bb.4 (align 8):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $r0, $r1, $r2, $r7, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2IT 11, 8, implicit-def $itstate
+ frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
+ renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
+ renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load 16 from constant-pool, align 8)
+ renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2
+ renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2
+
+ bb.2 (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
+
+ renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
+ MVE_VPST 4, implicit $vpr
+ renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r1, 11, 1, killed renamable $vpr
+ renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16, align 4)
+ renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0
+ renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr
+ t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3:
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+ bb.4 (align 8):
+ CONSTPOOL_ENTRY 0, %const.0, 16
+
+...
+---
+name: predvpt
+alignment: 8
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+ - id: 0
+ value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
+ alignment: 8
+ isTargetSpecific: false
+body: |
+ ; CHECK-LABEL: name: predvpt
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 11, 8, implicit-def $itstate
+ ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
+ ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load 16 from constant-pool, align 8)
+ ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2
+ ; CHECK: $lr = t2DLS killed renamable $lr
+ ; CHECK: bb.2 (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
+ ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
+ ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr
+ ; CHECK: MVE_VPST 8, implicit $vpr
+ ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16, align 4)
+ ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
+ ; CHECK: bb.3:
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+ ; CHECK: bb.4 (align 8):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $r0, $r1, $r2, $r7, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2IT 11, 8, implicit-def $itstate
+ frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
+ renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
+ renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load 16 from constant-pool, align 8)
+ renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2
+ renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2
+
+ bb.2 (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
+
+ MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
+ renamable $vpr = MVE_VCTP32 renamable $r2, 1, $vpr
+ MVE_VPST 8, implicit $vpr
+ renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16, align 4)
+ renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0
+ renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr
+ t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3:
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+ bb.4 (align 8):
+ CONSTPOOL_ENTRY 0, %const.0, 16
+...
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