[llvm-branch-commits] [llvm] e2006ed - [RISCV] Simplify vector instruction handling in RISCVMCInstLower.cpp.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-12-10T13:40:00-08:00
New Revision: e2006ed0f73e3d7c1545c506f26c330bcc59f60e

URL: https://github.com/llvm/llvm-project/commit/e2006ed0f73e3d7c1545c506f26c330bcc59f60e
DIFF: https://github.com/llvm/llvm-project/commit/e2006ed0f73e3d7c1545c506f26c330bcc59f60e.diff

LOG: [RISCV] Simplify vector instruction handling in RISCVMCInstLower.cpp.

Use RegisterClass::contains instead of going through getMinimalPhysRegClass
and hasSuperClassEq.

Remove the special case for NoRegister. It's identical to the
handling for any other regsiter that isn't VRM2/M4/M8.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
index da0725623b45..876d557ec79d 100644
--- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -160,17 +160,9 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
     case MachineOperand::MO_Register: {
       unsigned Reg = MO.getReg();
 
-      // Nothing to do on NoRegister operands (used as vector mask operand on
-      // unmasked instructions)
-      if (Reg == RISCV::NoRegister) {
-        MCOp = MCOperand::createReg(Reg);
-        break;
-      }
-
-      const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
-      if (RC->hasSuperClassEq(&RISCV::VRM2RegClass) ||
-          RC->hasSuperClassEq(&RISCV::VRM4RegClass) ||
-          RC->hasSuperClassEq(&RISCV::VRM8RegClass)) {
+      if (RISCV::VRM2RegClass.contains(Reg) ||
+          RISCV::VRM4RegClass.contains(Reg) ||
+          RISCV::VRM8RegClass.contains(Reg)) {
         Reg = TRI->getSubReg(Reg, RISCV::sub_vrm2);
         assert(Reg && "Subregister does not exist");
       }