[llvm-branch-commits] [llvm] 12406ad - [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
Sam Elliott via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Dec 10 11:30:56 PST 2020
Author: Sam Elliott
Date: 2020-12-10T19:25:51Z
New Revision: 12406ade0625ffa3939e2fa684293e02eb8791ff
URL: https://github.com/llvm/llvm-project/commit/12406ade0625ffa3939e2fa684293e02eb8791ff
DIFF: https://github.com/llvm/llvm-project/commit/12406ade0625ffa3939e2fa684293e02eb8791ff.diff
LOG: [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
There is an in-progress proposal for the following pseudo-instructions
in the assembler, to complement the existing `sext.w` rv64i instruction:
- sext.b
- sext.h
- zext.b
- zext.h
- zext.w
The `.b` and `.h` variants are available with rv32i and rv64i, and `zext.w` is
only available with `rv64i`.
These are implemented primarily as pseudo-instructions, as these instructions
expand to multiple real instructions. In the case of `zext.b`, this expands to a
single rv32/64i instruction, so it is implemented with an InstAlias (like
`sext.w` is on rv64i).
The proposal is available here: https://github.com/riscv/riscv-asm-manual/pull/61
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D92793
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/alu8.ll
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
llvm/test/CodeGen/RISCV/rv32Zbbp.ll
llvm/test/CodeGen/RISCV/rv64Zbbp.ll
llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
llvm/test/MC/RISCV/rv32i-aliases-invalid.s
llvm/test/MC/RISCV/rv32i-aliases-valid.s
llvm/test/MC/RISCV/rv64i-aliases-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 768b34ad45f1..aa483041e635 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -124,6 +124,10 @@ class RISCVAsmParser : public MCTargetAsmParser {
void emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
MCStreamer &Out, bool HasTmpReg);
+ // Helper to emit pseudo sign/zero extend instruction.
+ void emitPseudoExtend(MCInst &Inst, bool SignExtend, int64_t Width,
+ SMLoc IDLoc, MCStreamer &Out);
+
// Checks that a PseudoAddTPRel is using x4/tp in its second input operand.
// Enforcing this using a restricted register class for the second input
// operand of PseudoAddTPRel results in a poor diagnostic due to the fact
@@ -2269,6 +2273,35 @@ void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
Opcode, IDLoc, Out);
}
+void RISCVAsmParser::emitPseudoExtend(MCInst &Inst, bool SignExtend,
+ int64_t Width, SMLoc IDLoc,
+ MCStreamer &Out) {
+ // The sign/zero extend pseudo-instruction does two shifts, with the shift
+ // amounts dependent on the XLEN.
+ //
+ // The expansion looks like this
+ //
+ // SLLI rd, rs, XLEN - Width
+ // SR[A|R]I rd, rd, XLEN - Width
+ MCOperand DestReg = Inst.getOperand(0);
+ MCOperand SourceReg = Inst.getOperand(1);
+
+ unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI;
+ int64_t ShAmt = (isRV64() ? 64 : 32) - Width;
+
+ assert(ShAmt > 0 && "Shift amount must be non-zero.");
+
+ emitToStreamer(Out, MCInstBuilder(RISCV::SLLI)
+ .addOperand(DestReg)
+ .addOperand(SourceReg)
+ .addImm(ShAmt));
+
+ emitToStreamer(Out, MCInstBuilder(SecondOpcode)
+ .addOperand(DestReg)
+ .addOperand(DestReg)
+ .addImm(ShAmt));
+}
+
bool RISCVAsmParser::checkPseudoAddTPRel(MCInst &Inst,
OperandVector &Operands) {
assert(Inst.getOpcode() == RISCV::PseudoAddTPRel && "Invalid instruction");
@@ -2431,6 +2464,18 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
if (checkPseudoAddTPRel(Inst, Operands))
return true;
break;
+ case RISCV::PseudoSEXT_B:
+ emitPseudoExtend(Inst, /*SignExtend=*/true, /*Width=*/8, IDLoc, Out);
+ return false;
+ case RISCV::PseudoSEXT_H:
+ emitPseudoExtend(Inst, /*SignExtend=*/true, /*Width=*/16, IDLoc, Out);
+ return false;
+ case RISCV::PseudoZEXT_H:
+ emitPseudoExtend(Inst, /*SignExtend=*/false, /*Width=*/16, IDLoc, Out);
+ return false;
+ case RISCV::PseudoZEXT_W:
+ emitPseudoExtend(Inst, /*SignExtend=*/false, /*Width=*/32, IDLoc, Out);
+ return false;
}
emitToStreamer(Out, Inst);
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 9a24e28ad6e2..7a7b3bb0ad32 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -126,6 +126,7 @@ def HasStdExtZbbOrZbp
AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp)>;
def NotHasStdExtZbbOrZbp
: Predicate<"!(Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp())">;
+def NotHasStdExtZbb : Predicate<"!Subtarget->hasStdExtZbb()">;
def FeatureExtZbproposedc
: SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 768dd8a636fe..04e45f495e22 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -809,6 +809,8 @@ def : MnemonicAlias<"move", "mv">;
def : MnemonicAlias<"scall", "ecall">;
def : MnemonicAlias<"sbreak", "ebreak">;
+def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
+
//===----------------------------------------------------------------------===//
// Pseudo-instructions and codegen patterns
//
@@ -1055,6 +1057,25 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0,
def PseudoLA_TLS_GD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
"la.tls.gd", "$dst, $src">;
+
+/// Sign/Zero Extends
+
+// There are single-instruction versions of these in Zbb, so disable these
+// Pseudos if that extension is present.
+let Predicates = [NotHasStdExtZbb], hasSideEffects = 0, mayLoad = 0,
+ mayStore = 0, isCodeGenOnly = 0, isAsmParserOnly = 1 in {
+def PseudoSEXT_B : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "sext.b", "$rd, $rs">;
+def PseudoSEXT_H : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "sext.h", "$rd, $rs">;
+// rv64's sext.w is defined above, using InstAlias<"sext.w ...
+// zext.b is defined above, using InstAlias<"zext.b ...
+def PseudoZEXT_H : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.h", "$rd, $rs">;
+} // Predicates = [NotHasStdExtZbb], ...
+
+let Predicates = [NotHasStdExtZbb, IsRV64], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+ isCodeGenOnly = 0, isAsmParserOnly = 1 in {
+def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs">;
+} // Predicates = [NotHasStdExtZbb, IsRV64], ...
+
/// Loads
multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index a4c390091125..40dbe4e8f9a8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -480,12 +480,10 @@ def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>;
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZbb, IsRV32] in {
-def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>;
} // Predicates = [HasStdExtZbb, IsRV32]
let Predicates = [HasStdExtZbb, IsRV64] in {
-def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>;
def : InstAlias<"zext.w $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>;
} // Predicates = [HasStdExtZbb, IsRV64]
diff --git a/llvm/test/CodeGen/RISCV/alu8.ll b/llvm/test/CodeGen/RISCV/alu8.ll
index ed09174745b8..1462b1b70eb5 100644
--- a/llvm/test/CodeGen/RISCV/alu8.ll
+++ b/llvm/test/CodeGen/RISCV/alu8.ll
@@ -44,13 +44,13 @@ define i8 @slti(i8 %a) nounwind {
define i8 @sltiu(i8 %a) nounwind {
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: sltiu a0, a0, 3
; RV32I-NEXT: ret
;
; RV64I-LABEL: sltiu:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: sltiu a0, a0, 3
; RV64I-NEXT: ret
%1 = icmp ult i8 %a, 3
@@ -215,15 +215,15 @@ define i8 @slt(i8 %a, i8 %b) nounwind {
define i8 @sltu(i8 %a, i8 %b) nounwind {
; RV32I-LABEL: sltu:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a1, a1, 255
-; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: zext.b a1, a1
+; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sltu:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a1, a1, 255
-; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: zext.b a1, a1
+; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
%1 = icmp ult i8 %a, %b
@@ -248,13 +248,13 @@ define i8 @xor(i8 %a, i8 %b) nounwind {
define i8 @srl(i8 %a, i8 %b) nounwind {
; RV32I-LABEL: srl:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: srl a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: srl:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i8 %a, %b
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 6656e3d964d6..272af5604550 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -29,9 +29,9 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a3)
@@ -66,9 +66,9 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a3)
@@ -107,9 +107,9 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a3)
@@ -144,9 +144,9 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a3)
@@ -185,9 +185,9 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a3)
@@ -222,9 +222,9 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a3)
@@ -263,9 +263,9 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a3)
@@ -300,9 +300,9 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a3)
@@ -341,9 +341,9 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a2, (a3)
@@ -378,9 +378,9 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a2, (a3)
@@ -419,9 +419,9 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a3)
@@ -456,9 +456,9 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a3)
@@ -497,9 +497,9 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a2, (a3)
@@ -534,9 +534,9 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a2, (a3)
@@ -575,9 +575,9 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3)
@@ -612,9 +612,9 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3)
@@ -653,9 +653,9 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3)
@@ -690,9 +690,9 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3)
@@ -731,9 +731,9 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a4, zero, 255
; RV32IA-NEXT: sll a4, a4, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: andi a2, a2, 255
+; RV32IA-NEXT: zext.b a2, a2
; RV32IA-NEXT: sll a0, a2, a0
; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3)
@@ -768,9 +768,9 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: zext.b a2, a2
; RV64IA-NEXT: sllw a0, a2, a0
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3)
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index 62bdfce81504..3ba47fd1a4f2 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -26,7 +26,7 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
@@ -57,7 +57,7 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
@@ -92,7 +92,7 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
@@ -123,7 +123,7 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
@@ -158,7 +158,7 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
@@ -189,7 +189,7 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
@@ -224,7 +224,7 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
@@ -255,7 +255,7 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
@@ -290,7 +290,7 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2)
@@ -321,7 +321,7 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2)
@@ -356,7 +356,7 @@ define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
@@ -387,7 +387,7 @@ define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
@@ -422,7 +422,7 @@ define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
@@ -453,7 +453,7 @@ define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
@@ -488,7 +488,7 @@ define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
@@ -519,7 +519,7 @@ define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
@@ -554,7 +554,7 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
@@ -585,7 +585,7 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
@@ -620,7 +620,7 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2)
@@ -651,7 +651,7 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2)
@@ -686,7 +686,7 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
@@ -717,7 +717,7 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
@@ -752,7 +752,7 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
@@ -783,7 +783,7 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
@@ -818,7 +818,7 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
@@ -849,7 +849,7 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
@@ -884,7 +884,7 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
@@ -915,7 +915,7 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
@@ -950,7 +950,7 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2)
@@ -981,7 +981,7 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2)
@@ -1017,7 +1017,7 @@ define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w a1, a1, (a2)
@@ -1042,7 +1042,7 @@ define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w a1, a1, (a2)
@@ -1071,7 +1071,7 @@ define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
@@ -1096,7 +1096,7 @@ define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w.aq a1, a1, (a2)
@@ -1125,7 +1125,7 @@ define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
@@ -1150,7 +1150,7 @@ define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w.rl a1, a1, (a2)
@@ -1179,7 +1179,7 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
@@ -1204,7 +1204,7 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
@@ -1233,7 +1233,7 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: or a1, a3, a1
; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
@@ -1258,7 +1258,7 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: or a1, a3, a1
; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
@@ -1286,7 +1286,7 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
@@ -1318,7 +1318,7 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
@@ -1354,7 +1354,7 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
@@ -1386,7 +1386,7 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
@@ -1422,7 +1422,7 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2)
@@ -1454,7 +1454,7 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2)
@@ -1490,7 +1490,7 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2)
@@ -1522,7 +1522,7 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2)
@@ -1558,7 +1558,7 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2)
@@ -1590,7 +1590,7 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2)
@@ -1624,7 +1624,7 @@ define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -1645,7 +1645,7 @@ define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -1670,7 +1670,7 @@ define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -1691,7 +1691,7 @@ define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -1716,7 +1716,7 @@ define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -1737,7 +1737,7 @@ define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -1762,7 +1762,7 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -1783,7 +1783,7 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -1808,7 +1808,7 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -1829,7 +1829,7 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -1854,7 +1854,7 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -1875,7 +1875,7 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -1900,7 +1900,7 @@ define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -1921,7 +1921,7 @@ define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -1946,7 +1946,7 @@ define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -1967,7 +1967,7 @@ define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -1992,7 +1992,7 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -2013,7 +2013,7 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -2038,7 +2038,7 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV32IA-NEXT: srl a0, a1, a0
@@ -2059,7 +2059,7 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA-NEXT: srlw a0, a1, a0
@@ -3559,7 +3559,7 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB45_2
; RV32I-NEXT: .LBB45_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
@@ -3573,7 +3573,7 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB45_4
; RV32I-NEXT: .LBB45_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB45_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -3596,7 +3596,7 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6)
@@ -3624,7 +3624,7 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB45_2
; RV64I-NEXT: .LBB45_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
@@ -3638,7 +3638,7 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB45_4
; RV64I-NEXT: .LBB45_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB45_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -3661,7 +3661,7 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6)
@@ -3693,7 +3693,7 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB46_2
; RV32I-NEXT: .LBB46_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
@@ -3707,7 +3707,7 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB46_4
; RV32I-NEXT: .LBB46_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB46_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -3730,7 +3730,7 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6)
@@ -3758,7 +3758,7 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB46_2
; RV64I-NEXT: .LBB46_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
@@ -3772,7 +3772,7 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -3795,7 +3795,7 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6)
@@ -3827,7 +3827,7 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB47_2
; RV32I-NEXT: .LBB47_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
@@ -3841,7 +3841,7 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB47_4
; RV32I-NEXT: .LBB47_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB47_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -3864,7 +3864,7 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6)
@@ -3892,7 +3892,7 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB47_2
; RV64I-NEXT: .LBB47_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
@@ -3906,7 +3906,7 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB47_4
; RV64I-NEXT: .LBB47_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB47_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -3929,7 +3929,7 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6)
@@ -3961,7 +3961,7 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB48_2
; RV32I-NEXT: .LBB48_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
@@ -3975,7 +3975,7 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB48_4
; RV32I-NEXT: .LBB48_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB48_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -3998,7 +3998,7 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6)
@@ -4026,7 +4026,7 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB48_2
; RV64I-NEXT: .LBB48_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
@@ -4040,7 +4040,7 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB48_4
; RV64I-NEXT: .LBB48_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB48_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4063,7 +4063,7 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6)
@@ -4095,7 +4095,7 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB49_2
; RV32I-NEXT: .LBB49_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
@@ -4109,7 +4109,7 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB49_4
; RV32I-NEXT: .LBB49_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB49_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4132,7 +4132,7 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a6)
@@ -4160,7 +4160,7 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB49_2
; RV64I-NEXT: .LBB49_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
@@ -4174,7 +4174,7 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB49_4
; RV64I-NEXT: .LBB49_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB49_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4197,7 +4197,7 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a6)
@@ -4229,7 +4229,7 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB50_2
; RV32I-NEXT: .LBB50_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
@@ -4243,7 +4243,7 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4266,7 +4266,7 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6)
@@ -4294,7 +4294,7 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB50_2
; RV64I-NEXT: .LBB50_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
@@ -4308,7 +4308,7 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4331,7 +4331,7 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6)
@@ -4363,7 +4363,7 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB51_2
; RV32I-NEXT: .LBB51_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
@@ -4377,7 +4377,7 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4400,7 +4400,7 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6)
@@ -4428,7 +4428,7 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB51_2
; RV64I-NEXT: .LBB51_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
@@ -4442,7 +4442,7 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4465,7 +4465,7 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6)
@@ -4497,7 +4497,7 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB52_2
; RV32I-NEXT: .LBB52_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
@@ -4511,7 +4511,7 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4534,7 +4534,7 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6)
@@ -4562,7 +4562,7 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB52_2
; RV64I-NEXT: .LBB52_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
@@ -4576,7 +4576,7 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4599,7 +4599,7 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6)
@@ -4631,7 +4631,7 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB53_2
; RV32I-NEXT: .LBB53_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
@@ -4645,7 +4645,7 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4668,7 +4668,7 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6)
@@ -4696,7 +4696,7 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB53_2
; RV64I-NEXT: .LBB53_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
@@ -4710,7 +4710,7 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4733,7 +4733,7 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6)
@@ -4765,7 +4765,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: andi s1, a1, 255
+; RV32I-NEXT: zext.b s1, a1
; RV32I-NEXT: j .LBB54_2
; RV32I-NEXT: .LBB54_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
@@ -4779,7 +4779,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: andi a0, a3, 255
+; RV32I-NEXT: zext.b a0, a3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4802,7 +4802,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: andi a1, a1, 255
+; RV32IA-NEXT: zext.b a1, a1
; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a6)
@@ -4830,7 +4830,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: andi s1, a1, 255
+; RV64I-NEXT: zext.b s1, a1
; RV64I-NEXT: j .LBB54_2
; RV64I-NEXT: .LBB54_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
@@ -4844,7 +4844,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: andi a0, a3, 255
+; RV64I-NEXT: zext.b a0, a3
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
@@ -4867,7 +4867,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: zext.b a1, a1
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a6)
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
index f76c35252f02..8b7eecfc38d4 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
@@ -84,7 +84,7 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw t0, 4(sp)
; RV32I-FPELIM-NEXT: lw t1, 0(sp)
-; RV32I-FPELIM-NEXT: andi t2, a0, 255
+; RV32I-FPELIM-NEXT: zext.b t2, a0
; RV32I-FPELIM-NEXT: lui a0, 16
; RV32I-FPELIM-NEXT: addi a0, a0, -1
; RV32I-FPELIM-NEXT: and a0, a1, a0
@@ -108,7 +108,7 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw t0, 4(s0)
; RV32I-WITHFP-NEXT: lw t1, 0(s0)
-; RV32I-WITHFP-NEXT: andi t2, a0, 255
+; RV32I-WITHFP-NEXT: zext.b t2, a0
; RV32I-WITHFP-NEXT: lui a0, 16
; RV32I-WITHFP-NEXT: addi a0, a0, -1
; RV32I-WITHFP-NEXT: and a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
index f1fdd0de6730..b05115352cb3 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
@@ -50,7 +50,7 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f,
; RV64I: # %bb.0:
; RV64I-NEXT: lw t0, 8(sp)
; RV64I-NEXT: ld t1, 0(sp)
-; RV64I-NEXT: andi t2, a0, 255
+; RV64I-NEXT: zext.b t2, a0
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: and a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll b/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
index 5dcb3016f91d..ac060f9469ac 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
@@ -341,4 +341,3 @@ define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind {
%1 = call signext i32 @return_anyint32()
ret i32 %1
}
-
diff --git a/llvm/test/CodeGen/RISCV/rv32Zbbp.ll b/llvm/test/CodeGen/RISCV/rv32Zbbp.ll
index 0ae6d757287f..0b6b35ddea51 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbbp.ll
@@ -895,7 +895,7 @@ define i64 @packu_i64(i64 %a, i64 %b) nounwind {
define i32 @packh_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: packh_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
@@ -927,7 +927,7 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packh_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: slli a1, a2, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
diff --git a/llvm/test/CodeGen/RISCV/rv64Zbbp.ll b/llvm/test/CodeGen/RISCV/rv64Zbbp.ll
index f6787b833132..f2be24c6e478 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbbp.ll
@@ -732,7 +732,7 @@ define i64 @packu_i64(i64 %a, i64 %b) nounwind {
define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: packh_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
@@ -764,7 +764,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packh_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
index da7faa366e63..3ad524cbf0fc 100644
--- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
+++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
@@ -225,12 +225,12 @@ define i64 @zext_i1_to_i64(i1 %a) nounwind {
define i16 @zext_i8_to_i16(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: zext_i8_to_i16:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: ret
%1 = zext i8 %a to i16
ret i16 %1
@@ -239,12 +239,12 @@ define i16 @zext_i8_to_i16(i8 %a) nounwind {
define i32 @zext_i8_to_i32(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: zext_i8_to_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: ret
%1 = zext i8 %a to i32
ret i32 %1
@@ -253,13 +253,13 @@ define i32 @zext_i8_to_i32(i8 %a) nounwind {
define i64 @zext_i8_to_i64(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: andi a0, a0, 255
+; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
;
; RV64I-LABEL: zext_i8_to_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
+; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: ret
%1 = zext i8 %a to i64
ret i64 %1
diff --git a/llvm/test/MC/RISCV/rv32i-aliases-invalid.s b/llvm/test/MC/RISCV/rv32i-aliases-invalid.s
index ed680faa46cb..3c1e232d9378 100644
--- a/llvm/test/MC/RISCV/rv32i-aliases-invalid.s
+++ b/llvm/test/MC/RISCV/rv32i-aliases-invalid.s
@@ -11,6 +11,7 @@ li t4, foo # CHECK: :[[@LINE]]:8: error: immediate must be an integer i
negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
sll x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
srl x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
diff --git a/llvm/test/MC/RISCV/rv32i-aliases-valid.s b/llvm/test/MC/RISCV/rv32i-aliases-valid.s
index 5140fb2adfef..737dcee38fdb 100644
--- a/llvm/test/MC/RISCV/rv32i-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32i-aliases-valid.s
@@ -121,3 +121,19 @@ sb x10, (x11)
sh x10, (x11)
# CHECK-EXPAND: sw a0, 0(a1)
sw x10, (x11)
+
+# CHECK-EXPAND: slli a0, a1, 24
+# CHECK-EXPAND: srai a0, a0, 24
+sext.b x10, x11
+
+# CHECK-EXPAND: slli a0, a1, 16
+# CHECK-EXPAND: srai a0, a0, 16
+sext.h x10, x11
+
+# CHECK-INST: andi a0, a1, 255
+# CHECK-ALIAS: zext.b a0, a1
+zext.b x10, x11
+
+# CHECK-EXPAND: slli a0, a1, 16
+# CHECK-EXPAND: srli a0, a0, 16
+zext.h x10, x11
diff --git a/llvm/test/MC/RISCV/rv64i-aliases-valid.s b/llvm/test/MC/RISCV/rv64i-aliases-valid.s
index ec850ff35bb7..bcf4db813dde 100644
--- a/llvm/test/MC/RISCV/rv64i-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64i-aliases-valid.s
@@ -199,3 +199,23 @@ lwu x10, (x11)
ld x10, (x11)
# CHECK-EXPAND: sd a0, 0(a1)
sd x10, (x11)
+
+# CHECK-EXPAND: slli a0, a1, 56
+# CHECK-EXPAND: srai a0, a0, 56
+sext.b x10, x11
+
+# CHECK-EXPAND: slli a0, a1, 48
+# CHECK-EXPAND: srai a0, a0, 48
+sext.h x10, x11
+
+# CHECK-INST: andi a0, a1, 255
+# CHECK-ALIAS: zext.b a0, a1
+zext.b x10, x11
+
+# CHECK-EXPAND: slli a0, a1, 48
+# CHECK-EXPAND: srli a0, a0, 48
+zext.h x10, x11
+
+# CHECK-EXPAND: slli a0, a1, 32
+# CHECK-EXPAND: srli a0, a0, 32
+zext.w x10, x11
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