[llvm-branch-commits] [llvm] 846f576 - [RISCV] Add a table showing the layout of the fields in VTYPE. Rename MaskedOffAgnostic->MaskAgnostic. NFC

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-12-08T20:41:57-08:00
New Revision: 846f576bea4d0a55a4fe9190a2ac24cbb9d56a64

URL: https://github.com/llvm/llvm-project/commit/846f576bea4d0a55a4fe9190a2ac24cbb9d56a64
DIFF: https://github.com/llvm/llvm-project/commit/846f576bea4d0a55a4fe9190a2ac24cbb9d56a64.diff

LOG: [RISCV] Add a table showing the layout of the fields in VTYPE. Rename MaskedOffAgnostic->MaskAgnostic. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 6fe3f3324f7c..768b34ad45f1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -279,7 +279,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
     RISCVVSEW Sew;
     RISCVVLMUL Lmul;
     bool TailAgnostic;
-    bool MaskedoffAgnostic;
+    bool MaskAgnostic;
   };
 
   SMLoc StartLoc, EndLoc;
@@ -846,7 +846,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
 
   static std::unique_ptr<RISCVOperand>
   createVType(unsigned Sew, unsigned Lmul, bool Fractional, bool TailAgnostic,
-              bool MaskedoffAgnostic, SMLoc S, bool IsRV64) {
+              bool MaskAgnostic, SMLoc S, bool IsRV64) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::VType);
     unsigned SewLog2 = Log2_32(Sew / 8);
     unsigned LmulLog2 = Log2_32(Lmul);
@@ -858,7 +858,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
       Op->VType.Lmul = static_cast<RISCVVLMUL>(LmulLog2);
     }
     Op->VType.TailAgnostic = TailAgnostic;
-    Op->VType.MaskedoffAgnostic = MaskedoffAgnostic;
+    Op->VType.MaskAgnostic = MaskAgnostic;
     Op->StartLoc = S;
     Op->IsRV64 = IsRV64;
     return Op;
@@ -924,7 +924,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
   void addVTypeIOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     unsigned VTypeI = RISCVVType::encodeVTYPE(
-        VType.Lmul, VType.Sew, VType.TailAgnostic, VType.MaskedoffAgnostic);
+        VType.Lmul, VType.Sew, VType.TailAgnostic, VType.MaskAgnostic);
     Inst.addOperand(MCOperand::createImm(VTypeI));
   }
 
@@ -1612,11 +1612,11 @@ OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
 
   Name = getLexer().getTok().getIdentifier();
   // ma or mu
-  bool MaskedoffAgnostic;
+  bool MaskAgnostic;
   if (Name == "ma")
-    MaskedoffAgnostic = true;
+    MaskAgnostic = true;
   else if (Name == "mu")
-    MaskedoffAgnostic = false;
+    MaskAgnostic = false;
   else
     return MatchOperand_NoMatch;
   getLexer().Lex();
@@ -1625,7 +1625,7 @@ OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
     return MatchOperand_NoMatch;
 
   Operands.push_back(RISCVOperand::createVType(
-      Sew, Lmul, Fractional, TailAgnostic, MaskedoffAgnostic, S, isRV64()));
+      Sew, Lmul, Fractional, TailAgnostic, MaskAgnostic, S, isRV64()));
 
   return MatchOperand_Success;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2f2305bfb5d6..2c2ae54dbd59 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1953,7 +1953,7 @@ static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
   // For simplicity we reuse the vtype representation here.
   MIB.addImm(RISCVVType::encodeVTYPE(Multiplier, ElementWidth,
                                      /*TailAgnostic*/ false,
-                                     /*MaskedOffAgnostic*/ false));
+                                     /*MaskAgnostic*/ false));
 
   // Remove (now) redundant operands from pseudo
   MI.getOperand(SEWIndex).setImm(-1);

diff  --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
index 33892515d3f4..bf5c472ed072 100644
--- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -364,15 +364,25 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
 
 // Encode VTYPE into the binary format used by the the VSETVLI instruction which
 // is used by our MC layer representation.
+//
+// Bits | Name       | Description
+// -----+------------+------------------------------------------------
+// 7    | vma        | Vector mask agnostic
+// 6    | vta        | Vector tail agnostic
+// 5    | vlmul[2]   | Fractional lmul?
+// 4:2  | vsew[2:0]  | Standard element width (SEW) setting
+// 1:0  | vlmul[1:0] | Vector register group multiplier (LMUL) setting
+//
+// TODO: This format will change for the V extensions spec v1.0.
 inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW,
-                                   bool TailAgnostic, bool MaskedoffAgnostic) {
+                                   bool TailAgnostic, bool MaskAgnostic) {
   unsigned VLMULBits = static_cast<unsigned>(VLMUL);
   unsigned VSEWBits = static_cast<unsigned>(VSEW);
   unsigned VTypeI =
       ((VLMULBits & 0x4) << 3) | (VSEWBits << 2) | (VLMULBits & 0x3);
   if (TailAgnostic)
     VTypeI |= 0x40;
-  if (MaskedoffAgnostic)
+  if (MaskAgnostic)
     VTypeI |= 0x80;
 
   return VTypeI;