[llvm-branch-commits] [llvm] 49599cb - [PowerPC] Correct the bit-width definition for some imm operand in td.
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llvm-branch-commits at lists.llvm.org
Mon Dec 7 19:24:58 PST 2020
Author: Esme-Yi
Date: 2020-12-08T03:20:12Z
New Revision: 49599cb1a20cc4f4d6d2f71965f2069ae8d4f96a
URL: https://github.com/llvm/llvm-project/commit/49599cb1a20cc4f4d6d2f71965f2069ae8d4f96a
DIFF: https://github.com/llvm/llvm-project/commit/49599cb1a20cc4f4d6d2f71965f2069ae8d4f96a.diff
LOG: [PowerPC] Correct the bit-width definition for some imm operand in td.
Summary: The imm operands of some instructions are not defined accurately in td.
This is a small patch to correct these definitions.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D91603
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/MC/PowerPC/ppc64-errors.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 931109e2cbc4..82b868ec2b10 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -846,7 +846,7 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
"setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
}
-def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L),
+def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L),
"darn $RT, $L", IIC_LdStLD>, isPPC64;
def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
"addpcis $RT, $D", IIC_BrB, []>, isPPC64;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index c388ae75950f..849b96f507bd 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1928,7 +1928,7 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
PPC970_DGroup_Single;
-def DCBF : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
+def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst),
"dcbf $dst, $TH", IIC_LdStDCBF, []>,
PPC970_DGroup_Single;
@@ -2463,7 +2463,7 @@ let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
"stmw $rS, $dst", IIC_LdStLMW, []>;
-def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
+def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L),
"sync $L", IIC_LdStSync, []>;
let isCodeGenOnly = 1 in {
@@ -4309,7 +4309,7 @@ def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
"icbi $src", IIC_LdStICBI, []>;
-def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
+def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L),
"wait $L", IIC_LdStLoad, []>;
def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
@@ -4327,7 +4327,7 @@ def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
"mfsrin $RS, $RB", IIC_SprMFSR>;
-def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
+def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L),
"mtmsr $RS, $L", IIC_SprMTMSR>;
def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
@@ -4356,7 +4356,7 @@ def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
"mfmsr $RT", IIC_SprMFMSR, []>;
-def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
+def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L),
"mtmsrd $RS, $L", IIC_SprMTMSRD>;
def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
@@ -4376,11 +4376,11 @@ def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>;
let Predicates = [HasFPU] in {
let Defs = [RM] in {
def MTFSF : XFLForm_1<63, 711, (outs),
- (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
+ (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),
"mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
let Defs = [CR1] in
def MTFSF_rec : XFLForm_1<63, 711, (outs),
- (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
+ (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),
"mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm;
}
diff --git a/llvm/test/MC/PowerPC/ppc64-errors.s b/llvm/test/MC/PowerPC/ppc64-errors.s
index ef5d9e8e1e12..6da7406e2828 100644
--- a/llvm/test/MC/PowerPC/ppc64-errors.s
+++ b/llvm/test/MC/PowerPC/ppc64-errors.s
@@ -24,6 +24,44 @@
# CHECK-NEXT: subf 3, 4, symbol at tls
subf 3, 4, symbol at tls
+# Unsigned 1-bit immediate operands
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: mtmsr 1, 2
+ mtmsr 1, 2
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: mtmsrd 1, 2
+ mtmsrd 1, 2
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: mtfsf 1, 2, 2, 1
+ mtfsf 1, 2, 2, 1
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: mtfsf. 1, 2, 2, 1
+ mtfsf. 1, 2, 2, 1
+
+# Unsigned 2-bit immediate operands
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: darn 1, 4
+ darn 1, 4
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: wait 4
+ wait 4
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: sync 4
+ sync 4
+
+# Unsigned 3-bit immediate operands
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: dcbf 0, 1, 8
+ dcbf 0, 1, 8
+
# Signed 16-bit immediate operands
# CHECK: error: invalid operand for instruction
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