[llvm-branch-commits] [llvm] 55009a0 - [Test] Auto-update test checks

[Max Kazantsev via llvm-branch-commits]

Author: Max Kazantsev
Date: 2020-12-07T18:33:47+07:00
New Revision: 55009a0ff8bc3ff9ec91075726d44579dedaf8d3

URL: https://github.com/llvm/llvm-project/commit/55009a0ff8bc3ff9ec91075726d44579dedaf8d3
DIFF: https://github.com/llvm/llvm-project/commit/55009a0ff8bc3ff9ec91075726d44579dedaf8d3.diff

LOG: [Test] Auto-update test checks

Added: 
    

Modified: 
    llvm/test/Transforms/LoopStrengthReduce/X86/sibling-loops.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopStrengthReduce/X86/sibling-loops.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/sibling-loops.ll
index a69d6adc0f03..dd99b4ea1e0f 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/sibling-loops.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/sibling-loops.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -loop-reduce -S < %s | FileCheck %s
 ; We find it is very bad to allow LSR formula containing SCEVAddRecExpr Reg
 ; from siblings of current loop. When one loop is LSR optimized, it can
@@ -9,10 +10,75 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 @cond = common local_unnamed_addr global i64 0, align 8
 
 ; Check there is no extra lsr.iv generated in foo.
+define void @foo(i64 %N) local_unnamed_addr {
 ; CHECK-LABEL: @foo(
-; CHECK-NOT: lsr.iv{{[0-9]+}} =
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[DO_BODY:%.*]]
+; CHECK:       do.body:
+; CHECK-NEXT:    [[I_0:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[DO_BODY]] ]
+; CHECK-NEXT:    tail call void @goo(i64 [[I_0]], i64 [[I_0]])
+; CHECK-NEXT:    [[INC]] = add nuw nsw i64 [[I_0]], 1
+; CHECK-NEXT:    [[T0:%.*]] = load i64, i64* @cond, align 8
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i64 [[T0]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL]], label [[DO_BODY2_PREHEADER:%.*]], label [[DO_BODY]]
+; CHECK:       do.body2.preheader:
+; CHECK-NEXT:    br label [[DO_BODY2:%.*]]
+; CHECK:       do.body2:
+; CHECK-NEXT:    [[I_1:%.*]] = phi i64 [ [[INC3:%.*]], [[DO_BODY2]] ], [ 0, [[DO_BODY2_PREHEADER]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[INC]], [[I_1]]
+; CHECK-NEXT:    tail call void @goo(i64 [[I_1]], i64 [[TMP0]])
+; CHECK-NEXT:    [[INC3]] = add nuw nsw i64 [[I_1]], 1
+; CHECK-NEXT:    [[T1:%.*]] = load i64, i64* @cond, align 8
+; CHECK-NEXT:    [[TOBOOL6:%.*]] = icmp eq i64 [[T1]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL6]], label [[DO_BODY8_PREHEADER:%.*]], label [[DO_BODY2]]
+; CHECK:       do.body8.preheader:
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[INC]], [[INC3]]
+; CHECK-NEXT:    br label [[DO_BODY8:%.*]]
+; CHECK:       do.body8:
+; CHECK-NEXT:    [[I_2:%.*]] = phi i64 [ [[INC9:%.*]], [[DO_BODY8]] ], [ 0, [[DO_BODY8_PREHEADER]] ]
+; CHECK-NEXT:    [[J_2:%.*]] = phi i64 [ [[INC10:%.*]], [[DO_BODY8]] ], [ [[TMP1]], [[DO_BODY8_PREHEADER]] ]
+; CHECK-NEXT:    tail call void @goo(i64 [[I_2]], i64 [[J_2]])
+; CHECK-NEXT:    [[INC9]] = add nuw nsw i64 [[I_2]], 1
+; CHECK-NEXT:    [[INC10]] = add nsw i64 [[J_2]], 1
+; CHECK-NEXT:    [[T2:%.*]] = load i64, i64* @cond, align 8
+; CHECK-NEXT:    [[TOBOOL12:%.*]] = icmp eq i64 [[T2]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL12]], label [[DO_BODY14_PREHEADER:%.*]], label [[DO_BODY8]]
+; CHECK:       do.body14.preheader:
+; CHECK-NEXT:    br label [[DO_BODY14:%.*]]
+; CHECK:       do.body14:
+; CHECK-NEXT:    [[I_3:%.*]] = phi i64 [ [[INC15:%.*]], [[DO_BODY14]] ], [ 0, [[DO_BODY14_PREHEADER]] ]
+; CHECK-NEXT:    [[J_3:%.*]] = phi i64 [ [[INC16:%.*]], [[DO_BODY14]] ], [ [[INC10]], [[DO_BODY14_PREHEADER]] ]
+; CHECK-NEXT:    tail call void @goo(i64 [[I_3]], i64 [[J_3]])
+; CHECK-NEXT:    [[INC15]] = add nuw nsw i64 [[I_3]], 1
+; CHECK-NEXT:    [[INC16]] = add nsw i64 [[J_3]], 1
+; CHECK-NEXT:    [[T3:%.*]] = load i64, i64* @cond, align 8
+; CHECK-NEXT:    [[TOBOOL18:%.*]] = icmp eq i64 [[T3]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL18]], label [[DO_BODY20_PREHEADER:%.*]], label [[DO_BODY14]]
+; CHECK:       do.body20.preheader:
+; CHECK-NEXT:    br label [[DO_BODY20:%.*]]
+; CHECK:       do.body20:
+; CHECK-NEXT:    [[I_4:%.*]] = phi i64 [ [[INC21:%.*]], [[DO_BODY20]] ], [ 0, [[DO_BODY20_PREHEADER]] ]
+; CHECK-NEXT:    [[J_4:%.*]] = phi i64 [ [[INC22:%.*]], [[DO_BODY20]] ], [ [[INC16]], [[DO_BODY20_PREHEADER]] ]
+; CHECK-NEXT:    tail call void @goo(i64 [[I_4]], i64 [[J_4]])
+; CHECK-NEXT:    [[INC21]] = add nuw nsw i64 [[I_4]], 1
+; CHECK-NEXT:    [[INC22]] = add nsw i64 [[J_4]], 1
+; CHECK-NEXT:    [[T4:%.*]] = load i64, i64* @cond, align 8
+; CHECK-NEXT:    [[TOBOOL24:%.*]] = icmp eq i64 [[T4]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL24]], label [[DO_BODY26_PREHEADER:%.*]], label [[DO_BODY20]]
+; CHECK:       do.body26.preheader:
+; CHECK-NEXT:    br label [[DO_BODY26:%.*]]
+; CHECK:       do.body26:
+; CHECK-NEXT:    [[I_5:%.*]] = phi i64 [ [[INC27:%.*]], [[DO_BODY26]] ], [ 0, [[DO_BODY26_PREHEADER]] ]
+; CHECK-NEXT:    [[J_5:%.*]] = phi i64 [ [[INC28:%.*]], [[DO_BODY26]] ], [ [[INC22]], [[DO_BODY26_PREHEADER]] ]
+; CHECK-NEXT:    tail call void @goo(i64 [[I_5]], i64 [[J_5]])
+; CHECK-NEXT:    [[INC27]] = add nuw nsw i64 [[I_5]], 1
+; CHECK-NEXT:    [[INC28]] = add nsw i64 [[J_5]], 1
+; CHECK-NEXT:    [[T5:%.*]] = load i64, i64* @cond, align 8
+; CHECK-NEXT:    [[TOBOOL30:%.*]] = icmp eq i64 [[T5]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL30]], label [[DO_END31:%.*]], label [[DO_BODY26]]
+; CHECK:       do.end31:
+; CHECK-NEXT:    ret void
 ;
-define void @foo(i64 %N) local_unnamed_addr {
 entry:
   br label %do.body