[llvm-branch-commits] [llvm] 28fdeea - [PowerPC] Add support for intrinsics dcbfps and dcbstps in P10.
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Sun Dec 6 21:24:59 PST 2020
Author: Esme-Yi
Date: 2020-12-07T05:19:06Z
New Revision: 28fdeea9522fd2538773dc0d969dcb155b067e2e
URL: https://github.com/llvm/llvm-project/commit/28fdeea9522fd2538773dc0d969dcb155b067e2e
DIFF: https://github.com/llvm/llvm-project/commit/28fdeea9522fd2538773dc0d969dcb155b067e2e.diff
LOG: [PowerPC] Add support for intrinsics dcbfps and dcbstps in P10.
Summary: This patch added support for the intrinsics llvm.ppc.dcbfps and llvm.ppc.dcbstps.
dcbfps and dcbstps are actually extended mnemonics of dcbf.
dcbfps RA,RB ---> dcbf RA,RB,4
dcbstps RA,RB ---> dcbf RA,RB,6
Reviewed By: amyk, steven.zhang
Differential Revision: https://reviews.llvm.org/D91323
Added:
llvm/test/CodeGen/PowerPC/dcbf-p10.ll
Modified:
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index fa5000d42482..8db5c15fe761 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -18,10 +18,12 @@
let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
// dcba/dcbf/dcbi/dcbst/dcbt/dcbz/dcbzl(PPC970) instructions.
def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>;
- def int_ppc_dcbf : GCCBuiltin<"__builtin_dcbf">,
- Intrinsic<[], [llvm_ptr_ty], []>;
- def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], []>;
- def int_ppc_dcbflp: Intrinsic<[], [llvm_ptr_ty], []>;
+ def int_ppc_dcbf : GCCBuiltin<"__builtin_dcbf">,
+ Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
+ def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
+ def int_ppc_dcbflp : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
+ def int_ppc_dcbfps : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
+ def int_ppc_dcbstps : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty],
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 748716126836..2ff87c20ab25 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -774,12 +774,18 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
}
case PPC::DCBFx:
case PPC::DCBFL:
- case PPC::DCBFLP: {
+ case PPC::DCBFLP:
+ case PPC::DCBFPS:
+ case PPC::DCBSTPS: {
int L = 0;
if (Opcode == PPC::DCBFL)
L = 1;
else if (Opcode == PPC::DCBFLP)
L = 3;
+ else if (Opcode == PPC::DCBFPS)
+ L = 4;
+ else if (Opcode == PPC::DCBSTPS)
+ L = 6;
MCInst TmpInst;
TmpInst.setOpcode(PPC::DCBF);
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index 1a481efbc3b5..e77d7b3d892c 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -184,12 +184,18 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
if (MI->getOpcode() == PPC::DCBF) {
unsigned char L = MI->getOperand(0).getImm();
- if (!L || L == 1 || L == 3) {
- O << "\tdcbf";
- if (L == 1 || L == 3)
+ if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
+ O << "\tdcb";
+ if (L != 6)
+ O << "f";
+ if (L == 1)
O << "l";
if (L == 3)
- O << "p";
+ O << "lp";
+ if (L == 4)
+ O << "ps";
+ if (L == 6)
+ O << "stps";
O << " ";
printOperand(MI, 1, O);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 2dc575923da7..c388ae75950f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4609,6 +4609,16 @@ def : Pat<(int_ppc_dcbfl xoaddr:$dst),
def : Pat<(int_ppc_dcbflp xoaddr:$dst),
(DCBF 3, xoaddr:$dst)>;
+let Predicates = [IsISA3_1] in {
+ def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>;
+ def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>;
+
+ def : Pat<(int_ppc_dcbfps xoaddr:$dst),
+ (DCBF 4, xoaddr:$dst)>;
+ def : Pat<(int_ppc_dcbstps xoaddr:$dst),
+ (DCBF 6, xoaddr:$dst)>;
+}
+
def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
diff --git a/llvm/test/CodeGen/PowerPC/dcbf-p10.ll b/llvm/test/CodeGen/PowerPC/dcbf-p10.ll
new file mode 100644
index 000000000000..4e412358b818
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/dcbf-p10.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN: -ppc-vsr-nums-as-vr -mcpu=pwr10 | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s \
+; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN: -ppc-vsr-nums-as-vr -mcpu=pwr10 | FileCheck %s
+
+; Function Attrs: nounwind
+define void @dcbfps_test(i8* %a) {
+; CHECK-LABEL: dcbfps_test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi r3, r3, 3
+; CHECK-NEXT: dcbfps 0, r3
+; CHECK-NEXT: blr
+entry:
+ %add.a = getelementptr inbounds i8, i8* %a, i64 3
+ tail call void @llvm.ppc.dcbfps(i8* %add.a)
+ret void
+}
+
+declare void @llvm.ppc.dcbfps(i8*)
+
+; Function Attrs: nounwind
+define void @dcbstps_test(i8* %a) {
+; CHECK-LABEL: dcbstps_test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi r3, r3, 3
+; CHECK-NEXT: dcbstps 0, r3
+; CHECK-NEXT: blr
+entry:
+ %add.a = getelementptr inbounds i8, i8* %a, i64 3
+ tail call void @llvm.ppc.dcbstps(i8* %add.a)
+ret void
+}
+
+declare void @llvm.ppc.dcbstps(i8*)
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