[llvm-branch-commits] [llvm] 5fc8f90 - [RISCV] Replace a custom SDTypeProfile with SDTIntBinOp which should be sufficient here.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-12-05T20:18:22-08:00
New Revision: 5fc8f90f0a96a32b774cecc593af82959025906b

URL: https://github.com/llvm/llvm-project/commit/5fc8f90f0a96a32b774cecc593af82959025906b
DIFF: https://github.com/llvm/llvm-project/commit/5fc8f90f0a96a32b774cecc593af82959025906b.diff

LOG: [RISCV] Replace a custom SDTypeProfile with SDTIntBinOp which should be sufficient here.

On the surface this would be slightly less optimal for the isel
table, but due to a tablegen issue with HW mode this ends up
generating a smaller isel table.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 8d9748d80ba3..2f663cad82b8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -716,13 +716,10 @@ let Predicates = [HasStdExtZbs] in
 def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
           (SBEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
 
-def SDT_RISCVGREVGORC  : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>,
-                                              SDTCisSameAs<0, 1>,
-                                              SDTCisSameAs<1, 2>]>;
-def riscv_grevi    : SDNode<"RISCVISD::GREVI", SDT_RISCVGREVGORC, []>;
-def riscv_greviw   : SDNode<"RISCVISD::GREVIW", SDT_RISCVGREVGORC, []>;
-def riscv_gorci    : SDNode<"RISCVISD::GORCI", SDT_RISCVGREVGORC, []>;
-def riscv_gorciw   : SDNode<"RISCVISD::GORCIW", SDT_RISCVGREVGORC, []>;
+def riscv_grevi    : SDNode<"RISCVISD::GREVI", SDTIntBinOp, []>;
+def riscv_greviw   : SDNode<"RISCVISD::GREVIW", SDTIntBinOp, []>;
+def riscv_gorci    : SDNode<"RISCVISD::GORCI", SDTIntBinOp, []>;
+def riscv_gorciw   : SDNode<"RISCVISD::GORCIW", SDTIntBinOp, []>;
 
 let Predicates = [HasStdExtZbp] in {
 def : Pat<(riscv_grevi GPR:$rs1, timm:$shamt), (GREVI GPR:$rs1, timm:$shamt)>;