[llvm-branch-commits] [mlir] fa20ab7 - [mlir][PDL] Add append specialization for ByteCode OpCode to fix GCC5 build

[River Riddle via llvm-branch-commits]

Author: River Riddle
Date: 2020-12-01T17:13:16-08:00
New Revision: fa20ab7b1bb2c77570f46888fe46e6ecf7aeafc6

URL: https://github.com/llvm/llvm-project/commit/fa20ab7b1bb2c77570f46888fe46e6ecf7aeafc6
DIFF: https://github.com/llvm/llvm-project/commit/fa20ab7b1bb2c77570f46888fe46e6ecf7aeafc6.diff

LOG: [mlir][PDL] Add append specialization for ByteCode OpCode to fix GCC5 build

Added: 
    

Modified: 
    mlir/lib/Rewrite/ByteCode.cpp

Removed: 
    


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diff  --git a/mlir/lib/Rewrite/ByteCode.cpp b/mlir/lib/Rewrite/ByteCode.cpp
index ae5f322d2948..972f5097d4e7 100644
--- a/mlir/lib/Rewrite/ByteCode.cpp
+++ b/mlir/lib/Rewrite/ByteCode.cpp
@@ -265,6 +265,7 @@ struct ByteCodeWriter {
 
   /// Append a field to the bytecode.
   void append(ByteCodeField field) { bytecode.push_back(field); }
+  void append(OpCode opCode) { bytecode.push_back(opCode); }
 
   /// Append an address to the bytecode.
   void append(ByteCodeAddr field) {