[llvm-branch-commits] [llvm] 52533b5 - Revert "[InstCombine] Improve vector undef handling for sext(ashr(shl(trunc()))) fold"
Roman Lebedev via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Dec 1 04:52:22 PST 2020
Author: Roman Lebedev
Date: 2020-12-01T15:47:04+03:00
New Revision: 52533b52b868e055fe86061cf71a49601d0cbeb9
URL: https://github.com/llvm/llvm-project/commit/52533b52b868e055fe86061cf71a49601d0cbeb9
DIFF: https://github.com/llvm/llvm-project/commit/52533b52b868e055fe86061cf71a49601d0cbeb9.diff
LOG: Revert "[InstCombine] Improve vector undef handling for sext(ashr(shl(trunc()))) fold"
It seems i have missed checklines, temporairly reverting,
will reland momentairly..
This reverts commit aa1aa135097ecfab6d9917a435142030eff0a226.
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/test/Transforms/InstCombine/sext.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
index 6e94e5823433..59dae932ae49 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -1520,15 +1520,13 @@ Instruction *InstCombinerImpl::visitSExt(SExtInst &CI) {
Constant *BA = nullptr, *CA = nullptr;
if (match(Src, m_AShr(m_Shl(m_Trunc(m_Value(A)), m_Constant(BA)),
m_Constant(CA))) &&
- BA->isElementWiseEqual(CA) && A->getType() == DestTy) {
+ BA == CA && A->getType() == DestTy) {
Constant *WideCurrShAmt = ConstantExpr::getSExt(CA, DestTy);
Constant *NumLowbitsLeft = ConstantExpr::getSub(
ConstantInt::get(DestTy, SrcTy->getScalarSizeInBits()), WideCurrShAmt);
Constant *NewShAmt = ConstantExpr::getSub(
ConstantInt::get(DestTy, DestTy->getScalarSizeInBits()),
NumLowbitsLeft);
- NewShAmt =
- Constant::mergeUndefsWith(Constant::mergeUndefsWith(NewShAmt, BA), CA);
A = Builder.CreateShl(A, NewShAmt, CI.getName());
return BinaryOperator::CreateAShr(A, NewShAmt);
}
diff --git a/llvm/test/Transforms/InstCombine/sext.ll b/llvm/test/Transforms/InstCombine/sext.ll
index ebab23a19525..319c07d9f8a9 100644
--- a/llvm/test/Transforms/InstCombine/sext.ll
+++ b/llvm/test/Transforms/InstCombine/sext.ll
@@ -167,8 +167,10 @@ define <2 x i32> @test10_vec_nonuniform(<2 x i32> %i) {
define <2 x i32> @test10_vec_undef0(<2 x i32> %i) {
; CHECK-LABEL: @test10_vec_undef0(
-; CHECK-NEXT: [[D1:%.*]] = shl <2 x i32> [[I:%.*]], <i32 30, i32 undef>
-; CHECK-NEXT: [[D:%.*]] = ashr <2 x i32> [[D1]], <i32 30, i32 undef>
+; CHECK-NEXT: [[A:%.*]] = trunc <2 x i32> [[I:%.*]] to <2 x i8>
+; CHECK-NEXT: [[B:%.*]] = shl <2 x i8> [[A]], <i8 6, i8 0>
+; CHECK-NEXT: [[C:%.*]] = ashr <2 x i8> [[B]], <i8 6, i8 undef>
+; CHECK-NEXT: [[D:%.*]] = sext <2 x i8> [[C]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[D]]
;
%A = trunc <2 x i32> %i to <2 x i8>
@@ -179,8 +181,10 @@ define <2 x i32> @test10_vec_undef0(<2 x i32> %i) {
}
define <2 x i32> @test10_vec_undef1(<2 x i32> %i) {
; CHECK-LABEL: @test10_vec_undef1(
-; CHECK-NEXT: [[D1:%.*]] = shl <2 x i32> [[I:%.*]], <i32 30, i32 undef>
-; CHECK-NEXT: [[D:%.*]] = ashr <2 x i32> [[D1]], <i32 30, i32 undef>
+; CHECK-NEXT: [[A:%.*]] = trunc <2 x i32> [[I:%.*]] to <2 x i8>
+; CHECK-NEXT: [[B:%.*]] = shl <2 x i8> [[A]], <i8 6, i8 undef>
+; CHECK-NEXT: [[C:%.*]] = ashr <2 x i8> [[B]], <i8 6, i8 0>
+; CHECK-NEXT: [[D:%.*]] = sext <2 x i8> [[C]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[D]]
;
%A = trunc <2 x i32> %i to <2 x i8>
@@ -191,8 +195,8 @@ define <2 x i32> @test10_vec_undef1(<2 x i32> %i) {
}
define <2 x i32> @test10_vec_undef2(<2 x i32> %i) {
; CHECK-LABEL: @test10_vec_undef2(
-; CHECK-NEXT: [[D1:%.*]] = shl <2 x i32> [[I:%.*]], <i32 30, i32 undef>
-; CHECK-NEXT: [[D:%.*]] = ashr <2 x i32> [[D1]], <i32 30, i32 undef>
+; CHECK-NEXT: [[D1:%.*]] = shl <2 x i32> [[I:%.*]], <i32 30, i32 24>
+; CHECK-NEXT: [[D:%.*]] = ashr <2 x i32> [[D1]], <i32 30, i32 24>
; CHECK-NEXT: ret <2 x i32> [[D]]
;
%A = trunc <2 x i32> %i to <2 x i8>
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