[llvm-branch-commits] [llvm-branch] r371378 - Merging r371305 and r371307:

Mon Sep 9 02:36:49 PDT 2019

Author: hans
Date: Mon Sep  9 02:36:49 2019
New Revision: 371378

URL: http://llvm.org/viewvc/llvm-project?rev=371378&view=rev
Log:
Merging r371305 and r371307:

------------------------------------------------------------------------
r371305 | nikic | 2019-09-07 14:03:48 +0200 (Sat, 07 Sep 2019) | 1 line

[X86] Add test for PR43230; NFC
------------------------------------------------------------------------

------------------------------------------------------------------------
r371307 | nikic | 2019-09-07 14:13:44 +0200 (Sat, 07 Sep 2019) | 9 lines

[X86] Fix pshuflw formation from repeated shuffle mask (PR43230)

Fix for https://bugs.llvm.org/show_bug.cgi?id=43230.

When creating PSHUFLW from a repeated shuffle mask, we have to apply
the checks to the repeated mask, not the original one. For the test
case from PR43230 the inspected part of the original mask is all undef.

Differential Revision: https://reviews.llvm.org/D67314
------------------------------------------------------------------------

Modified:
    llvm/branches/release_90/   (props changed)
    llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/release_90/test/CodeGen/X86/vector-shuffle-256-v16.ll

Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------

--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Sep  9 02:36:49 2019
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368164,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369310,369426,369443,369886,370036,370176,370204,370271,370355,370404,370426,370430,370720-370721,370753,371048,371088,371095,371111,371262
+/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368164,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369310,369426,369443,369886,370036,370176,370204,370271,370355,370404,370426,370430,370720-370721,370753,371048,371088,371095,371111,371262,371305,371307

Modified: llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp?rev=371378&r1=371377&r2=371378&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp Mon Sep  9 02:36:49 2019
@@ -31664,8 +31664,8 @@ static bool matchUnaryPermuteShuffle(MVT
   if (!ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == 16) {
     SmallVector<int, 4> RepeatedMask;
     if (is128BitLaneRepeatedShuffleMask(MaskEltVT, Mask, RepeatedMask)) {
-      ArrayRef<int> LoMask(Mask.data() + 0, 4);
-      ArrayRef<int> HiMask(Mask.data() + 4, 4);
+      ArrayRef<int> LoMask(RepeatedMask.data() + 0, 4);
+      ArrayRef<int> HiMask(RepeatedMask.data() + 4, 4);
 
       // PSHUFLW: permute lower 4 elements only.
       if (isUndefOrInRange(LoMask, 0, 4) &&

Modified: llvm/branches/release_90/test/CodeGen/X86/vector-shuffle-256-v16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/X86/vector-shuffle-256-v16.ll?rev=371378&r1=371377&r2=371378&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/X86/vector-shuffle-256-v16.ll (original)
+++ llvm/branches/release_90/test/CodeGen/X86/vector-shuffle-256-v16.ll Mon Sep  9 02:36:49 2019
@@ -4754,3 +4754,44 @@ define <16 x i16> @unpckh_v16i16(<16 x i
   ret <16 x i16> %unpckh
 }
 
+define <16 x i16> @pr43230(<16 x i16> %a, <16 x i16> %b) {
+; AVX1-LABEL: pr43230:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
+; AVX1-NEXT:    vpsllw $12, %xmm1, %xmm2
+; AVX1-NEXT:    vpsllw $4, %xmm1, %xmm1
+; AVX1-NEXT:    vpor %xmm2, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddw %xmm1, %xmm1, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT:    vpsrlw $8, %xmm0, %xmm3
+; AVX1-NEXT:    vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
+; AVX1-NEXT:    vpsrlw $4, %xmm0, %xmm1
+; AVX1-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpsrlw $2, %xmm0, %xmm1
+; AVX1-NEXT:    vpaddw %xmm2, %xmm2, %xmm2
+; AVX1-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpsrlw $1, %xmm0, %xmm1
+; AVX1-NEXT:    vpaddw %xmm2, %xmm2, %xmm2
+; AVX1-NEXT:    vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; AVX1-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: pr43230:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} ymm1 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
+; AVX2-NEXT:    vpunpckhwd {{.*#+}} ymm0 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
+; AVX2-NEXT:    vpsrlvd %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,ymm0[26,27],zero,zero
+; AVX2-NEXT:    retq
+;
+; AVX512VL-LABEL: pr43230:
+; AVX512VL:       # %bb.0:
+; AVX512VL-NEXT:    vpsrlvw %ymm1, %ymm0, %ymm0
+; AVX512VL-NEXT:    vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512VL-NEXT:    retq
+  %shr = lshr <16 x i16> %a, %b
+  %shuf = shufflevector <16 x i16> zeroinitializer, <16 x i16> %shr, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15>
+  ret <16 x i16> %shuf
+}


