[llvm-branch-commits] [llvm-branch] r371044 - Merging r370720 and r370721:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Sep 5 02:57:35 PDT 2019
Author: hans
Date: Thu Sep 5 02:57:35 2019
New Revision: 371044
URL: http://llvm.org/viewvc/llvm-project?rev=371044&view=rev
Log:
Merging r370720 and r370721:
------------------------------------------------------------------------
r370720 | bjope | 2019-09-03 11:33:40 +0200 (Tue, 03 Sep 2019) | 13 lines
[LV] Precommit test case showing miscompile from PR43166. NFC
Summary: Precommit test case showing miscompile from PR43166.
Reviewers: fhahn, Ayal
Reviewed By: fhahn
Subscribers: rkruppe, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67072
------------------------------------------------------------------------
------------------------------------------------------------------------
r370721 | bjope | 2019-09-03 11:33:55 +0200 (Tue, 03 Sep 2019) | 20 lines
[LV] Fix miscompiles by adding non-header PHI nodes to AllowedExit
Summary:
Fold-tail currently supports reduction last-vector-value live-out's,
but has yet to support last-scalar-value live-outs, including
non-header phi's. As it relies on AllowedExit in order to detect
them and bail out we need to add the non-header PHI nodes to
AllowedExit, otherwise we end up with miscompiles.
Solves https://bugs.llvm.org/show_bug.cgi?id=43166
Reviewers: fhahn, Ayal
Reviewed By: fhahn, Ayal
Subscribers: anna, hiraditya, rkruppe, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67074
------------------------------------------------------------------------
Added:
llvm/branches/release_90/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
- copied, changed from r370720, llvm/trunk/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll
Modified:
llvm/branches/release_90/ (props changed)
llvm/branches/release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
llvm/branches/release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Sep 5 02:57:35 2019
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368164,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369310,369426,369443,369886,370036,370176,370204,370271,370355,370404,370753
+/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368164,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369310,369426,369443,369886,370036,370176,370204,370271,370355,370404,370720-370721,370753
Modified: llvm/branches/release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h?rev=371044&r1=371043&r2=371044&view=diff
==============================================================================
--- llvm/branches/release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h (original)
+++ llvm/branches/release_90/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h Thu Sep 5 02:57:35 2019
@@ -452,8 +452,8 @@ private:
/// Holds the widest induction type encountered.
Type *WidestIndTy = nullptr;
- /// Allowed outside users. This holds the induction and reduction
- /// vars which can be accessed from outside the loop.
+ /// Allowed outside users. This holds the variables that can be accessed from
+ /// outside the loop.
SmallPtrSet<Value *, 4> AllowedExit;
/// Can we assume the absence of NaNs.
Modified: llvm/branches/release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp?rev=371044&r1=371043&r2=371044&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp (original)
+++ llvm/branches/release_90/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp Thu Sep 5 02:57:35 2019
@@ -631,6 +631,7 @@ bool LoopVectorizationLegality::canVecto
// Unsafe cyclic dependencies with header phis are identified during
// legalization for reduction, induction and first order
// recurrences.
+ AllowedExit.insert(&I);
continue;
}
Copied: llvm/branches/release_90/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll (from r370720, llvm/trunk/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll?p2=llvm/branches/release_90/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll&p1=llvm/trunk/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll&r1=370720&r2=371044&rev=371044&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll (original)
+++ llvm/branches/release_90/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll Thu Sep 5 02:57:35 2019
@@ -33,40 +33,16 @@
; the result is "BAD!"
-; FIXME: The result here is incorrect! See https://bugs.llvm.org/show_bug.cgi?id=43166
+; This test case miscompiled with clang 8.0.0 (see PR43166), now we get
+; loop not vectorized: Cannot fold tail by masking in the presence of live outs.
+; instead.
define i64 @test1(i64 %y) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
-; CHECK: vector.ph:
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> undef, i64 [[Y:%.*]], i32 0
-; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> undef, <4 x i32> zeroinitializer
-; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[INDEX]], i32 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i64> [[BROADCAST_SPLAT2]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i64> <i64 3, i64 3, i64 3, i64 3>, [[BROADCAST_SPLAT2]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ule <4 x i32> [[INDUCTION]], <i32 2, i32 2, i32 2, i32 2>
-; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i1> [[TMP1]], <i1 true, i1 true, i1 true, i1 true>
-; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i1> [[TMP4]], [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i1> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> <i64 77, i64 77, i64 77, i64 77>, <4 x i64> [[TMP2]]
-; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4
-; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0
-; CHECK: middle.block:
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i64> [[PREDPHI]], i32 3
-; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
-; CHECK: scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 4, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[COND_END:%.*]] ]
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[Y]], 0
+; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[COND_END:%.*]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[Y:%.*]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[COND_END]], label [[COND_FALSE:%.*]]
; CHECK: cond.false:
; CHECK-NEXT: [[DIV:%.*]] = xor i64 3, [[Y]]
@@ -75,9 +51,9 @@ define i64 @test1(i64 %y) {
; CHECK-NEXT: [[COND:%.*]] = phi i64 [ [[DIV]], [[COND_FALSE]] ], [ 77, [[FOR_BODY]] ]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 3
-; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop !2
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]]
; CHECK: for.cond.cleanup:
-; CHECK-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], [[COND_END]] ], [ [[TMP8]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], [[COND_END]] ]
; CHECK-NEXT: ret i64 [[COND_LCSSA]]
;
entry:
@@ -102,40 +78,16 @@ for.cond.cleanup:
ret i64 %cond
}
-
-; FIXME: The result here is incorrect! See https://bugs.llvm.org/show_bug.cgi?id=43166
+; This test case miscompiled with clang 8.0.0 (see PR43166), now we get
+; loop not vectorized: Cannot fold tail by masking in the presence of live outs.
+; instead.
define i64 @test2(i64 %y) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
-; CHECK: vector.ph:
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> undef, i64 [[Y:%.*]], i32 0
-; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> undef, <4 x i32> zeroinitializer
-; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[INDEX]], i32 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i64> [[BROADCAST_SPLAT2]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ule <4 x i32> [[INDUCTION]], <i32 2, i32 2, i32 2, i32 2>
-; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i1> [[TMP1]], <i1 true, i1 true, i1 true, i1 true>
-; CHECK-NEXT: [[TMP4:%.*]] = and <4 x i1> [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i1> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP5]], <4 x i64> <i64 77, i64 77, i64 77, i64 77>, <4 x i64> <i64 55, i64 55, i64 55, i64 55>
-; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4
-; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !4
-; CHECK: middle.block:
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[PREDPHI]], i32 3
-; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
-; CHECK: scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 4, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[COND_END:%.*]] ]
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[Y]], 0
+; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[COND_END:%.*]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[Y:%.*]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[COND_END]], label [[COND_FALSE:%.*]]
; CHECK: cond.false:
; CHECK-NEXT: br label [[COND_END]]
@@ -143,9 +95,9 @@ define i64 @test2(i64 %y) {
; CHECK-NEXT: [[COND:%.*]] = phi i64 [ 55, [[COND_FALSE]] ], [ 77, [[FOR_BODY]] ]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 3
-; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop !5
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]]
; CHECK: for.cond.cleanup:
-; CHECK-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], [[COND_END]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], [[COND_END]] ]
; CHECK-NEXT: ret i64 [[COND_LCSSA]]
;
entry:
@@ -169,38 +121,16 @@ for.cond.cleanup:
ret i64 %cond
}
-
-; FIXME: The result here is incorrect! See https://bugs.llvm.org/show_bug.cgi?id=43166
+; This test case miscompiled with clang 8.0.0 (see PR43166), now we get
+; loop not vectorized: Cannot fold tail by masking in the presence of live outs.
+; instead.
define i32 @test3(i64 %y) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
-; CHECK: vector.ph:
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> undef, i64 [[Y:%.*]], i32 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> undef, <4 x i32> zeroinitializer
-; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = icmp eq <4 x i64> [[BROADCAST_SPLAT]], zeroinitializer
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i32> [[VEC_IND]], <i32 2, i32 2, i32 2, i32 2>
-; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i1> [[TMP0]], <i1 true, i1 true, i1 true, i1 true>
-; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i1> [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = and <4 x i1> [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[VEC_IND]], <4 x i32> <i32 55, i32 55, i32 55, i32 55>
-; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
-; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4
-; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !6
-; CHECK: middle.block:
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3
-; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
-; CHECK: scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 4, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[COND_END:%.*]] ]
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[Y]], 0
+; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[COND_END:%.*]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[Y:%.*]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[COND_END]], label [[COND_FALSE:%.*]]
; CHECK: cond.false:
; CHECK-NEXT: br label [[COND_END]]
@@ -208,9 +138,9 @@ define i32 @test3(i64 %y) {
; CHECK-NEXT: [[COND:%.*]] = phi i32 [ 55, [[COND_FALSE]] ], [ [[I]], [[FOR_BODY]] ]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 3
-; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop !7
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]]
; CHECK: for.cond.cleanup:
-; CHECK-NEXT: [[COND_LCSSA:%.*]] = phi i32 [ [[COND]], [[COND_END]] ], [ [[TMP6]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[COND_LCSSA:%.*]] = phi i32 [ [[COND]], [[COND_END]] ]
; CHECK-NEXT: ret i32 [[COND_LCSSA]]
;
entry:
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