[llvm-branch-commits] [llvm-branch] r374433 - [9.0 branch][ARM] VFPv2 only supports 16 D registers.
Tom Stellard via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Oct 10 12:44:38 PDT 2019
Author: tstellar
Date: Thu Oct 10 12:44:38 2019
New Revision: 374433
URL: http://llvm.org/viewvc/llvm-project?rev=374433&view=rev
Log:
[9.0 branch][ARM] VFPv2 only supports 16 D registers.
Summary:
Patch for 9.0.1.
Simplified version of r372186/r372187: fix the meaning of the "vfpv2" and "vfpv2sp" features, but keep around the useless "vfp2d16" and "vfp2d16sp" features, to reduce the risk on the release branch.
Fixes https://bugs.llvm.org/show_bug.cgi?id=43365
Reviewers: t.p.northover, tstellar
Reviewed By: t.p.northover
Subscribers: kristof.beyls, hiraditya, kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68675
Modified:
llvm/branches/release_90/lib/Support/ARMTargetParser.cpp
llvm/branches/release_90/lib/Target/ARM/ARM.td
llvm/branches/release_90/test/MC/ARM/vfp-aliases-diagnostics.s
Modified: llvm/branches/release_90/lib/Support/ARMTargetParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Support/ARMTargetParser.cpp?rev=374433&r1=374432&r2=374433&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Support/ARMTargetParser.cpp (original)
+++ llvm/branches/release_90/lib/Support/ARMTargetParser.cpp Thu Oct 10 12:44:38 2019
@@ -176,10 +176,10 @@ bool ARM::getFPUFeatures(unsigned FPUKin
// exist).
{"+fpregs", "-fpregs", FPUVersion::VFPV2, FPURestriction::SP_D16},
- {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::None},
+ {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
{"+vfp2d16", "-vfp2d16", FPUVersion::VFPV2, FPURestriction::D16},
{"+vfp2d16sp", "-vfp2d16sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
- {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::None},
+ {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
{"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
{"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
{"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
@@ -195,7 +195,7 @@ bool ARM::getFPUFeatures(unsigned FPUKin
{"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
{"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
{"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
- {"+d32", "-d32", FPUVersion::VFPV2, FPURestriction::None},
+ {"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
};
for (const auto &Info: FPUFeatureInfoList) {
Modified: llvm/branches/release_90/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/ARM/ARM.td?rev=374433&r1=374432&r2=374433&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/ARM/ARM.td (original)
+++ llvm/branches/release_90/lib/Target/ARM/ARM.td Thu Oct 10 12:44:38 2019
@@ -57,12 +57,15 @@ def FeatureD32 : SubtargetFea
"Extend FP to 32 double registers">;
multiclass VFPver<string name, string query, string description,
- list<SubtargetFeature> prev = [],
- list<SubtargetFeature> otherimplies = []> {
+ list<SubtargetFeature> prev,
+ list<SubtargetFeature> otherimplies,
+ list<SubtargetFeature> vfp2prev = []> {
def _D16_SP: SubtargetFeature<
name#"d16sp", query#"D16SP", "true",
description#" with only 16 d-registers and no double precision",
- !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # otherimplies>;
+ !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
+ !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
+ otherimplies>;
def _SP: SubtargetFeature<
name#"sp", query#"SP", "true",
description#" with no double precision",
@@ -72,6 +75,7 @@ multiclass VFPver<string name, string qu
name#"d16", query#"D16", "true",
description#" with only 16 d-registers",
!foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #
+ vfp2prev #
otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
def "": SubtargetFeature<
name, query, "true", description,
@@ -80,11 +84,23 @@ multiclass VFPver<string name, string qu
!cast<SubtargetFeature>(NAME # "_SP")]>;
}
-defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions",
- [], [FeatureFPRegs]>;
+def FeatureVFP2_D16_SP : SubtargetFeature<"vfp2d16sp", "HasVFPv2D16SP", "true",
+ "Enable VFP2 instructions with "
+ "no double precision",
+ [FeatureFPRegs]>;
+def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
+ "Enable VFP2 instructions with "
+ "no double precision",
+ [FeatureVFP2_D16_SP]>;
+def FeatureVFP2_D16 : SubtargetFeature<"vfp2d16", "HasVFPv2D16", "true",
+ "Enable VFP2 instructions",
+ [FeatureFP64, FeatureVFP2_D16_SP]>;
+def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
+ "Enable VFP2 instructions",
+ [FeatureVFP2_D16, FeatureVFP2_SP]>;
defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
- [FeatureVFP2]>;
+ [], [], [FeatureVFP2]>;
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
"Enable NEON instructions",
@@ -98,7 +114,7 @@ defm FeatureVFP4: VFPver<"vfp4", "HasVFP
[FeatureVFP3], [FeatureFP16]>;
defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
- [FeatureVFP4]>;
+ [FeatureVFP4], []>;
def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
"Enable full half-precision "
Modified: llvm/branches/release_90/test/MC/ARM/vfp-aliases-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/MC/ARM/vfp-aliases-diagnostics.s?rev=374433&r1=374432&r2=374433&view=diff
==============================================================================
--- llvm/branches/release_90/test/MC/ARM/vfp-aliases-diagnostics.s (original)
+++ llvm/branches/release_90/test/MC/ARM/vfp-aliases-diagnostics.s Thu Oct 10 12:44:38 2019
@@ -13,17 +13,17 @@ aliases:
fldmeax sp!, {s0}
@ CHECK-LABEL: aliases
-@ CHECK: error: operand must be a list of registers in range [d0, d31]
+@ CHECK: error: operand must be a list of registers in range [d0, d15]
@ CHECK: fstmeax sp!, {s0}
@ CHECK: ^
-@ CHECK: error: operand must be a list of registers in range [d0, d31]
+@ CHECK: error: operand must be a list of registers in range [d0, d15]
@ CHECK: fldmfdx sp!, {s0}
@ CHECK: ^
-@ CHECK: error: operand must be a list of registers in range [d0, d31]
+@ CHECK: error: operand must be a list of registers in range [d0, d15]
@ CHECK: fstmfdx sp!, {s0}
@ CHECK: ^
-@ CHECK: error: operand must be a list of registers in range [d0, d31]
+@ CHECK: error: operand must be a list of registers in range [d0, d15]
@ CHECK: fldmeax sp!, {s0}
@ CHECK: ^
@@ -31,16 +31,16 @@ aliases:
fstmiaxhs r0, {s0}
fstmiaxls r0, {s0}
fstmiaxvs r0, {s0}
-@ CHECK: error: operand must be a list of registers in range [d0, d31]
+@ CHECK: error: operand must be a list of registers in range [d0, d15]
@ CHECK: fstmiaxcs r0, {s0}
@ CHECK: ^
-@ CHECK: error: operand must be a list of registers in range [d0, d31]
+@ CHECK: error: operand must be a list of registers in range [d0, d15]
@ CHECK: fstmiaxhs r0, {s0}
@ CHECK: ^
-@ CHECK: error: operand must be a list of registers in range [d0, d31]
+@ CHECK: error: operand must be a list of registers in range [d0, d15]
@ CHECK: fstmiaxls r0, {s0}
@ CHECK: ^
-@ CHECK: error: operand must be a list of registers in range [d0, d31]
+@ CHECK: error: operand must be a list of registers in range [d0, d15]
@ CHECK: fstmiaxvs r0, {s0}
@ CHECK: ^
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