[llvm-branch-commits] [llvm-branch] r352682 - [docs][mips] 8.0 Release notes

[Simon Atanasyan via llvm-branch-commits]

Author: atanasyan
Date: Wed Jan 30 14:45:12 2019
New Revision: 352682

URL: http://llvm.org/viewvc/llvm-project?rev=352682&view=rev
Log:
[docs][mips] 8.0 Release notes

MIPS specific part of LLVM 8.0 Release notes.

Differential Revision: http://reviews.llvm.org/D57457

Modified:
    llvm/branches/release_80/docs/ReleaseNotes.rst

Modified: llvm/branches/release_80/docs/ReleaseNotes.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/docs/ReleaseNotes.rst?rev=352682&r1=352681&r2=352682&view=diff
==============================================================================
--- llvm/branches/release_80/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_80/docs/ReleaseNotes.rst Wed Jan 30 14:45:12 2019
@@ -52,6 +52,8 @@ Non-comprehensive list of changes in thi
   from a dll are accessed via a stub, to allow the linker to convert it to
   a dllimport if needed.
 
+* Added support for labels as offsets in ``.reloc`` directive.
+
 .. NOTE
    If you would like to document a larger change, then you can add a
    subsection about it right here. You can copy the following boilerplate
@@ -82,8 +84,23 @@ Changes to the ARM Backend
 Changes to the MIPS Target
 --------------------------
 
- During this release ...
+* Improved support of GlobalISel instruction selection framework.
+
+* Implemented emission of ``R_MIPS_JALR`` and ``R_MICROMIPS_JALR``
+  relocations. These relocations provide hints to a linker for optimization
+  of jumps to protected symbols.
+
+* ORC JIT has been supported for MIPS and MIPS64 architectures.
+
+* Assembler now suggests alternative MIPS instruction mnemonics when
+  an invalid one is specified.
+
+* Improved support for MIPS N32 ABI.
+
+* Added new instructions (``pll.ps``, ``plu.ps``, ``cvt.s.pu``,
+  ``cvt.s.pl``, ``cvt.ps``, ``sigrie``).
 
+* Numerous bug fixes and code cleanups.
 
 Changes to the PowerPC Target
 -----------------------------