[llvm-branch-commits] [llvm-branch] r354260 - Merging r354034 and r354117:

Mon Feb 18 03:21:42 PST 2019

Author: hans
Date: Mon Feb 18 03:21:42 2019
New Revision: 354260

URL: http://llvm.org/viewvc/llvm-project?rev=354260&view=rev
Log:
Merging r354034 and r354117:

------------------------------------------------------------------------
r354034 | rksimon | 2019-02-14 15:45:32 +0100 (Thu, 14 Feb 2019) | 1 line

[X86][AVX] Add PR40730 test case
------------------------------------------------------------------------

------------------------------------------------------------------------
r354117 | rksimon | 2019-02-15 12:39:21 +0100 (Fri, 15 Feb 2019) | 9 lines

[X86][AVX] lowerShuffleAsLanePermuteAndPermute - fully populate the lane shuffle mask (PR40730)

As detailed on PR40730, we are not correctly filling in the lane shuffle mask (D53148/rL344446) - we fill in for the correct src lane but don't add it to the correct mask element, so any reference to the correct element is likely to see an UNDEF mask index.

This allows constant folding to propagate UNDEFs prior to the lane mask being (correctly) lowered to vperm2f128.

This patch fixes the issue by fully populating the lane shuffle mask - this is more than is necessary (if we only filled in the required mask elements we might be able to match other shuffle instructions - broadcasts etc.), but its the most cautious approach as this needs to be cherrypicked into the 8.0.0 release branch.

Differential Revision: https://reviews.llvm.org/D58237
------------------------------------------------------------------------

Added:
    llvm/branches/release_80/test/CodeGen/X86/pr40730.ll
      - copied, changed from r354034, llvm/trunk/test/CodeGen/X86/pr40730.ll
Modified:
    llvm/branches/release_80/   (props changed)
    llvm/branches/release_80/lib/Target/X86/X86ISelLowering.cpp

Propchange: llvm/branches/release_80/
------------------------------------------------------------------------------

--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Feb 18 03:21:42 2019
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,351322,351325,351344-351345,351349,351351,351370,351381,351387,351421,351426,351436,351475,351485,351753-351754,351765,351910,351930,351932,352034,352204,352246,352374,352555,352607-352608,352707,352714,352770,352886,352889,352892,352895,352908,352917,352935,352945,353015,353061,353082,353138,353141,353155,353213,353218,353304,353308,353334,353367,353374,353383,353463,353480,353489,353551,353733,353758,353809,353907,354128,354131,354144
+/llvm/trunk:155241,351322,351325,351344-351345,351349,351351,351370,351381,351387,351421,351426,351436,351475,351485,351753-351754,351765,351910,351930,351932,352034,352204,352246,352374,352555,352607-352608,352707,352714,352770,352886,352889,352892,352895,352908,352917,352935,352945,353015,353061,353082,353138,353141,353155,353213,353218,353304,353308,353334,353367,353374,353383,353463,353480,353489,353551,353733,353758,353809,353907,354034,354117,354128,354131,354144

Modified: llvm/branches/release_80/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/lib/Target/X86/X86ISelLowering.cpp?rev=354260&r1=354259&r2=354260&view=diff
==============================================================================
--- llvm/branches/release_80/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_80/lib/Target/X86/X86ISelLowering.cpp Mon Feb 18 03:21:42 2019
@@ -13884,7 +13884,6 @@ static SDValue lowerVectorShuffleAsLaneP
   int NumEltsPerLane = NumElts / NumLanes;
 
   SmallVector<int, 4> SrcLaneMask(NumLanes, SM_SentinelUndef);
-  SmallVector<int, 16> LaneMask(NumElts, SM_SentinelUndef);
   SmallVector<int, 16> PermMask(NumElts, SM_SentinelUndef);
 
   for (int i = 0; i != NumElts; ++i) {
@@ -13899,10 +13898,20 @@ static SDValue lowerVectorShuffleAsLaneP
       return SDValue();
     SrcLaneMask[DstLane] = SrcLane;
 
-    LaneMask[i] = (SrcLane * NumEltsPerLane) + (i % NumEltsPerLane);
     PermMask[i] = (DstLane * NumEltsPerLane) + (M % NumEltsPerLane);
   }
 
+  // Make sure we set all elements of the lane mask, to avoid undef propagation.
+  SmallVector<int, 16> LaneMask(NumElts, SM_SentinelUndef);
+  for (int DstLane = 0; DstLane != NumLanes; ++DstLane) {
+    int SrcLane = SrcLaneMask[DstLane];
+    if (0 <= SrcLane)
+      for (int j = 0; j != NumEltsPerLane; ++j) {
+        LaneMask[(DstLane * NumEltsPerLane) + j] =
+            (SrcLane * NumEltsPerLane) + j;
+      }
+  }
+
   // If we're only shuffling a single lowest lane and the rest are identity
   // then don't bother.
   // TODO - isShuffleMaskInputInPlace could be extended to something like this.

Copied: llvm/branches/release_80/test/CodeGen/X86/pr40730.ll (from r354034, llvm/trunk/test/CodeGen/X86/pr40730.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/test/CodeGen/X86/pr40730.ll?p2=llvm/branches/release_80/test/CodeGen/X86/pr40730.ll&p1=llvm/trunk/test/CodeGen/X86/pr40730.ll&r1=354034&r2=354260&rev=354260&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr40730.ll (original)
+++ llvm/branches/release_80/test/CodeGen/X86/pr40730.ll Mon Feb 18 03:21:42 2019
@@ -19,7 +19,7 @@ define <8 x i32> @shuffle_v8i32_0dcd3f14
 ; CHECK:      .LCPI1_0:
 ; CHECK-NEXT: .quad   60129542157
 ; CHECK-NEXT: .quad   60129542157
-; CHECK-NEXT: .zero   8
+; CHECK-NEXT: .quad   68719476736
 ; CHECK-NEXT: .quad   60129542157
 
 define <8 x i32> @shuffle_v8i32_0dcd3f14_constant(<8 x i32> %a0)  {


