[llvm-branch-commits] [llvm-branch] r323434 - Merging r323369 and r323371:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Thu Jan 25 07:28:01 2018
New Revision: 323434

URL: http://llvm.org/viewvc/llvm-project?rev=323434&view=rev
Log:
Merging r323369 and r323371:

------------------------------------------------------------------------
r323369 | aemerson | 2018-01-24 20:59:29 +0100 (Wed, 24 Jan 2018) | 4 lines

[GlobalISel] Don't fall back to FastISel.

Apparently checking the pass structure isn't enough to ensure that we don't fall
back to FastISel, as it's set up as part of the SelectionDAGISel.
------------------------------------------------------------------------

------------------------------------------------------------------------
r323371 | aemerson | 2018-01-24 21:35:37 +0100 (Wed, 24 Jan 2018) | 12 lines

[AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load.

The tablegen imported patterns for sext(load(a)) don't check for single uses
of the load or delete the original after matching. As a result two loads are
left in the generated code. This particular issue will be fixed by adding
support for a G_SEXTLOAD opcode in future.

There are however other potential issues around this that wouldn't be fixed by
a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile
loads at all in the AArch64 selector.

Fixes/works around PR36018.
------------------------------------------------------------------------

Added:
    llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll
      - copied unchanged from r323369, llvm/trunk/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll
    llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
      - copied unchanged from r323371, llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
Modified:
    llvm/branches/release_60/   (props changed)
    llvm/branches/release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/branches/release_60/lib/CodeGen/TargetPassConfig.cpp
    llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp

Propchange: llvm/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Jan 25 07:28:01 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321980,321991,321993-321994,322003,322053,322056,322103,322106,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323190,323307
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321980,321991,321993-321994,322003,322053,322056,322103,322106,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323190,323307,323369,323371

Modified: llvm/branches/release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=323434&r1=323433&r2=323434&view=diff
==============================================================================
--- llvm/branches/release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/branches/release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jan 25 07:28:01 2018
@@ -1380,8 +1380,10 @@ void SelectionDAGISel::SelectAllBasicBlo
   FastISelFailed = false;
   // Initialize the Fast-ISel state, if needed.
   FastISel *FastIS = nullptr;
-  if (TM.Options.EnableFastISel)
+  if (TM.Options.EnableFastISel) {
+    DEBUG(dbgs() << "Enabling fast-isel\n");
     FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
+  }
 
   setupSwiftErrorVals(Fn, TLI, FuncInfo);
 

Modified: llvm/branches/release_60/lib/CodeGen/TargetPassConfig.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/CodeGen/TargetPassConfig.cpp?rev=323434&r1=323433&r2=323434&view=diff
==============================================================================
--- llvm/branches/release_60/lib/CodeGen/TargetPassConfig.cpp (original)
+++ llvm/branches/release_60/lib/CodeGen/TargetPassConfig.cpp Thu Jan 25 07:28:01 2018
@@ -717,6 +717,8 @@ bool TargetPassConfig::addCoreISelPasses
   if (EnableGlobalISel == cl::BOU_TRUE ||
       (EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled() &&
        EnableFastISelOption != cl::BOU_TRUE)) {
+    TM->setFastISel(false);
+
     if (addIRTranslator())
       return true;
 

Modified: llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=323434&r1=323433&r2=323434&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Jan 25 07:28:01 2018
@@ -929,6 +929,12 @@ bool AArch64InstructionSelector::select(
       return false;
     }
 
+    // FIXME: PR36018: Volatile loads in some cases are incorrectly selected by
+    // folding with an extend. Until we have a G_SEXTLOAD solution bail out if
+    // we hit one.
+    if (Opcode == TargetOpcode::G_LOAD && MemOp.isVolatile())
+      return false;
+
     const unsigned PtrReg = I.getOperand(1).getReg();
 #ifndef NDEBUG
     const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);