[llvm-branch-commits] [compiler-rt-branch] r323338 - Merging r323315:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jan 24 07:56:18 PST 2018
Author: hans
Date: Wed Jan 24 07:56:18 2018
New Revision: 323338
URL: http://llvm.org/viewvc/llvm-project?rev=323338&view=rev
Log:
Merging r323315:
------------------------------------------------------------------------
r323315 | mstorsjo | 2018-01-24 11:14:52 +0100 (Wed, 24 Jan 2018) | 9 lines
[builtins] Align addresses to cache lines in __clear_cache for aarch64
This makes sure that the last cache line gets invalidated properly.
This matches the example code at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html,
and also matches what libgcc does.
Differential Revision: https://reviews.llvm.org/D42196
------------------------------------------------------------------------
Modified:
compiler-rt/branches/release_60/ (props changed)
compiler-rt/branches/release_60/lib/builtins/clear_cache.c
Propchange: compiler-rt/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jan 24 07:56:18 2018
@@ -1 +1 @@
-/compiler-rt/trunk:323039
+/compiler-rt/trunk:323039,323315
Modified: compiler-rt/branches/release_60/lib/builtins/clear_cache.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_60/lib/builtins/clear_cache.c?rev=323338&r1=323337&r2=323338&view=diff
==============================================================================
--- compiler-rt/branches/release_60/lib/builtins/clear_cache.c (original)
+++ compiler-rt/branches/release_60/lib/builtins/clear_cache.c Wed Jan 24 07:56:18 2018
@@ -163,12 +163,14 @@ void __clear_cache(void *start, void *en
* uintptr_t in case this runs in an IPL32 environment.
*/
const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
- for (addr = xstart; addr < xend; addr += dcache_line_size)
+ for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
+ addr += dcache_line_size)
__asm __volatile("dc cvau, %0" :: "r"(addr));
__asm __volatile("dsb ish");
const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
- for (addr = xstart; addr < xend; addr += icache_line_size)
+ for (addr = xstart & ~(icache_line_size - 1); addr < xend;
+ addr += icache_line_size)
__asm __volatile("ic ivau, %0" :: "r"(addr));
__asm __volatile("isb sy");
#elif defined (__powerpc64__)
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