[llvm-branch-commits] [llvm-branch] r325591 - Merging r325550:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Feb 20 08:18:57 PST 2018
Author: hans
Date: Tue Feb 20 08:18:57 2018
New Revision: 325591
URL: http://llvm.org/viewvc/llvm-project?rev=325591&view=rev
Log:
Merging r325550:
I couldn't get fp16-copy-gpr.mir to pass after merging so I removed it until
aemerson; the other test I re-generated and it seems to work.
------------------------------------------------------------------------
r325550 | aemerson | 2018-02-20 06:11:57 +0100 (Tue, 20 Feb 2018) | 7 lines
[AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.
This is a follow on commit to r[x] where we fix the other direction of copy.
For this case, after converting the source from gpr32 -> fpr32, we use a
subregister copy, which is essentially what EXTRACT_SUBREG does in SDAG land.
https://reviews.llvm.org/D43444
------------------------------------------------------------------------
Removed:
llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp
Propchange: llvm/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 20 08:18:57 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325550
Modified: llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=325591&r1=325590&r2=325591&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp Tue Feb 20 08:18:57 2018
@@ -315,12 +315,39 @@ static unsigned selectLoadStoreUIOp(unsi
return GenericOpc;
}
+static bool selectFP16CopyFromGPR32(MachineInstr &I, const TargetInstrInfo &TII,
+ MachineRegisterInfo &MRI, unsigned SrcReg) {
+ // Copies from gpr32 to fpr16 need to use a sub-register copy.
+ unsigned CopyReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::COPY))
+ .addDef(CopyReg)
+ .addUse(SrcReg);
+ unsigned SubRegCopy = MRI.createVirtualRegister(&AArch64::FPR16RegClass);
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY))
+ .addDef(SubRegCopy)
+ .addUse(CopyReg, 0, AArch64::hsub);
+
+ MachineOperand &RegOp = I.getOperand(1);
+ RegOp.setReg(SubRegCopy);
+ return true;
+}
+
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) {
unsigned DstReg = I.getOperand(0).getReg();
+ unsigned SrcReg = I.getOperand(1).getReg();
+
if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+ if (TRI.getRegClass(AArch64::FPR16RegClassID)->contains(DstReg) &&
+ !TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
+ const RegisterBank &RegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
+ const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(
+ MRI.getType(SrcReg), RegBank, RBI, /* GetAllRegSet */ true);
+ if (SrcRC == &AArch64::GPR32allRegClass)
+ return selectFP16CopyFromGPR32(I, TII, MRI, SrcReg);
+ }
assert(I.isCopy() && "Generic operators do not allow physical registers");
return true;
}
@@ -328,7 +355,6 @@ static bool selectCopy(MachineInstr &I,
const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
(void)DstSize;
- unsigned SrcReg = I.getOperand(1).getReg();
const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
(void)SrcSize;
assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) &&
@@ -355,9 +381,7 @@ static bool selectCopy(MachineInstr &I,
}
if (!TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
- const RegClassOrRegBank &RegClassOrBank =
- MRI.getRegClassOrRegBank(SrcReg);
-
+ const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(SrcReg);
const TargetRegisterClass *SrcRC =
RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
const RegisterBank *RB = nullptr;
@@ -376,6 +400,9 @@ static bool selectCopy(MachineInstr &I,
.addImm(AArch64::hsub);
MachineOperand &RegOp = I.getOperand(1);
RegOp.setReg(PromoteReg);
+ } else if (RC == &AArch64::FPR16RegClass &&
+ SrcRC == &AArch64::GPR32allRegClass) {
+ selectFP16CopyFromGPR32(I, TII, MRI, SrcReg);
}
}
Removed: llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir?rev=325590&view=auto
==============================================================================
--- llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir (original)
+++ llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir (removed)
@@ -1,90 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -o - -global-isel -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s
-
-# PR36345
---- |
- target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64-arm-none-eabi"
-
- %struct.struct2 = type { [2 x half] }
-
- @global_arg0 = common dso_local global %struct.struct2 zeroinitializer, align 2
-
- ; Function Attrs: noinline nounwind optnone
- define dso_local void @c_test([2 x half], [2 x half]* %addr) {
- ; CHECK-LABEL: name: c_test
- ; CHECK: bb.0 (%ir-block.1):
- ; CHECK: liveins: %h0, %h1, %x0
- ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY %h1
- ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
- ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32
- ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 0, 15
- ; CHECK: [[SUBREG_TO_REG2:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG2]]
- ; CHECK: [[SUBREG_TO_REG3:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY3]], %subreg.sub_32
- ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[BFMXri]], [[SUBREG_TO_REG3]], 48, 15
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMXri1]]
- ; CHECK: [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0
- ; CHECK: STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2)
- ; CHECK: RET_ReallyLR
- store [2 x half] %0, [2 x half]* %addr, align 2
- ret void
- }
-...
----
-name: c_test
-alignment: 2
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: fpr }
- - { id: 2, class: fpr }
- - { id: 3, class: gpr }
- - { id: 4, class: gpr }
- - { id: 5, class: gpr }
- - { id: 6, class: gpr }
- - { id: 7, class: gpr }
- - { id: 8, class: gpr }
- - { id: 9, class: gpr }
- - { id: 10, class: gpr }
- - { id: 11, class: gpr }
- - { id: 12, class: gpr }
-body: |
- bb.1 (%ir-block.1):
- liveins: %h0, %h1, %x0
-
- ; CHECK-LABEL: name: c_test
- ; CHECK: liveins: %h0, %h1, %x0
- ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY %h1
- ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
- ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32
- ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 0, 15
- ; CHECK: [[SUBREG_TO_REG2:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG2]]
- ; CHECK: [[SUBREG_TO_REG3:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY3]], %subreg.sub_32
- ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[BFMXri]], [[SUBREG_TO_REG3]], 48, 15
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMXri1]]
- ; CHECK: [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0
- ; CHECK: STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2)
- ; CHECK: RET_ReallyLR
- %1:fpr(s16) = COPY %h0
- %2:fpr(s16) = COPY %h1
- %3:gpr(s32) = G_IMPLICIT_DEF
- %11:gpr(s16) = COPY %1(s16)
- %4:gpr(s32) = G_INSERT %3, %11(s16), 0
- %12:gpr(s16) = COPY %2(s16)
- %5:gpr(s32) = G_INSERT %4, %12(s16), 16
- %0:gpr(s32) = COPY %5(s32)
- %6:gpr(p0) = COPY %x0
- G_STORE %0(s32), %6(p0) :: (store 4 into %ir.addr, align 2)
- RET_ReallyLR
-
-...
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