[llvm-branch-commits] [llvm-branch] r325586 - Merging r325463:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Feb 20 07:49:15 PST 2018
Author: hans
Date: Tue Feb 20 07:49:15 2018
New Revision: 325586
URL: http://llvm.org/viewvc/llvm-project?rev=325586&view=rev
Log:
Merging r325463:
(I had to re-generate the test and manually update to handle the r323922 MIR physical register sigil.
------------------------------------------------------------------------
r325463 | aemerson | 2018-02-18 18:10:49 +0100 (Sun, 18 Feb 2018) | 8 lines
[AArch64][GlobalISel] Fix an assert fail/miscompile when fp16 types are copied
to gpr register banks.
PR36345.
rdar://36478867
Differential Revision: https://reviews.llvm.org/D43310
------------------------------------------------------------------------
Added:
llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
- copied, changed from r325463, llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp
Propchange: llvm/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 20 07:49:15 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463
Modified: llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=325586&r1=325585&r2=325586&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/branches/release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp Tue Feb 20 07:49:15 2018
@@ -354,6 +354,31 @@ static bool selectCopy(MachineInstr &I,
return false;
}
+ if (!TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
+ const RegClassOrRegBank &RegClassOrBank =
+ MRI.getRegClassOrRegBank(SrcReg);
+
+ const TargetRegisterClass *SrcRC =
+ RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
+ const RegisterBank *RB = nullptr;
+ if (!SrcRC) {
+ RB = RegClassOrBank.get<const RegisterBank *>();
+ SrcRC = getRegClassForTypeOnBank(MRI.getType(SrcReg), *RB, RBI, true);
+ }
+ // Copies from fpr16 to gpr32 need to use SUBREG_TO_REG.
+ if (RC == &AArch64::GPR32allRegClass && SrcRC == &AArch64::FPR16RegClass) {
+ unsigned PromoteReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
+ BuildMI(*I.getParent(), I, I.getDebugLoc(),
+ TII.get(AArch64::SUBREG_TO_REG))
+ .addDef(PromoteReg)
+ .addImm(0)
+ .addUse(SrcReg)
+ .addImm(AArch64::hsub);
+ MachineOperand &RegOp = I.getOperand(1);
+ RegOp.setReg(PromoteReg);
+ }
+ }
+
// No need to constrain SrcReg. It will get constrained when
// we hit another of its use or its defs.
// Copies do not have constraints.
Copied: llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir (from r325463, llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir?p2=llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir&p1=llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir&r1=325463&r2=325586&rev=325586&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir (original)
+++ llvm/branches/release_60/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir Tue Feb 20 07:49:15 2018
@@ -12,6 +12,24 @@
; Function Attrs: noinline nounwind optnone
define dso_local void @c_test([2 x half], [2 x half]* %addr) {
+ ; CHECK-LABEL: name: c_test
+ ; CHECK: bb.0 (%ir-block.1):
+ ; CHECK: liveins: %h0, %h1, %x0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY %h1
+ ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
+ ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
+ ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
+ ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32
+ ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 0, 15
+ ; CHECK: [[SUBREG_TO_REG2:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
+ ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG2]]
+ ; CHECK: [[SUBREG_TO_REG3:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY3]], %subreg.sub_32
+ ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[BFMXri]], [[SUBREG_TO_REG3]], 48, 15
+ ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMXri1]]
+ ; CHECK: [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0
+ ; CHECK: STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2)
+ ; CHECK: RET_ReallyLR
store [2 x half] %0, [2 x half]* %addr, align 2
ret void
}
@@ -38,31 +56,34 @@ registers:
- { id: 12, class: gpr }
body: |
bb.1 (%ir-block.1):
- liveins: $h0, $h1, $x0
+ liveins: %h0, %h1, %x0
; CHECK-LABEL: name: c_test
- ; CHECK: liveins: $h0, $h1, $x0
- ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
- ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+ ; CHECK: liveins: %h0, %h1, %x0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY %h1
+ ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
- ; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 15
- ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]]
- ; CHECK: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 15
- ; CHECK: [[COPY4:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRWui [[BFMWri1]], [[COPY4]], 0 :: (store 4 into %ir.addr, align 2)
+ ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32
+ ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 0, 15
+ ; CHECK: [[SUBREG_TO_REG2:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
+ ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG2]]
+ ; CHECK: [[SUBREG_TO_REG3:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY3]], %subreg.sub_32
+ ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[BFMXri]], [[SUBREG_TO_REG3]], 48, 15
+ ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMXri1]]
+ ; CHECK: [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0
+ ; CHECK: STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2)
; CHECK: RET_ReallyLR
- %1:fpr(s16) = COPY $h0
- %2:fpr(s16) = COPY $h1
+ %1:fpr(s16) = COPY %h0
+ %2:fpr(s16) = COPY %h1
%3:gpr(s32) = G_IMPLICIT_DEF
%11:gpr(s16) = COPY %1(s16)
%4:gpr(s32) = G_INSERT %3, %11(s16), 0
%12:gpr(s16) = COPY %2(s16)
%5:gpr(s32) = G_INSERT %4, %12(s16), 16
%0:gpr(s32) = COPY %5(s32)
- %6:gpr(p0) = COPY $x0
+ %6:gpr(p0) = COPY %x0
G_STORE %0(s32), %6(p0) :: (store 4 into %ir.addr, align 2)
RET_ReallyLR
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