[llvm-branch-commits] [llvm-branch] r339859 - Merging r339769:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Thu Aug 16 03:13:29 2018
New Revision: 339859

URL: http://llvm.org/viewvc/llvm-project?rev=339859&view=rev
Log:
Merging r339769:
------------------------------------------------------------------------
r339769 | nemanjai | 2018-08-15 14:58:13 +0200 (Wed, 15 Aug 2018) | 12 lines

[PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types

When trying to combine a DAG that builds a vector out of sign-extensions of
vector extracts, the code assumes legal input types. Due to that, we have to
disable this combine prior to legalization.
In some cases, the DAG will look slightly different after legalization so
account for that in the matching code.

This is a fix for https://bugs.llvm.org/show_bug.cgi?id=38087

Differential Revision: https://reviews.llvm.org/D49080

------------------------------------------------------------------------

Added:
    llvm/branches/release_70/test/CodeGen/PowerPC/pr38087.ll
      - copied, changed from r339769, llvm/trunk/test/CodeGen/PowerPC/pr38087.ll
Modified:
    llvm/branches/release_70/   (props changed)
    llvm/branches/release_70/lib/Target/PowerPC/PPCISelLowering.cpp

Propchange: llvm/branches/release_70/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Aug 16 03:13:29 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338902,338915,338968,339073,339166,339179,339184,339190,339225,339316,339319,339411,339492,339533,339535-339536,339600,339636
+/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338902,338915,338968,339073,339166,339179,339184,339190,339225,339316,339319,339411,339492,339533,339535-339536,339600,339636,339769

Modified: llvm/branches/release_70/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/PowerPC/PPCISelLowering.cpp?rev=339859&r1=339858&r2=339859&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/release_70/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 16 03:13:29 2018
@@ -12007,10 +12007,15 @@ static SDValue combineBVOfVecSExt(SDNode
   auto isSExtOfVecExtract = [&](SDValue Op) -> bool {
     if (!Op)
       return false;
-    if (Op.getOpcode() != ISD::SIGN_EXTEND)
+    if (Op.getOpcode() != ISD::SIGN_EXTEND &&
+        Op.getOpcode() != ISD::SIGN_EXTEND_INREG)
       return false;
 
+    // A SIGN_EXTEND_INREG might be fed by an ANY_EXTEND to produce a value
+    // of the right width.
     SDValue Extract = Op.getOperand(0);
+    if (Extract.getOpcode() == ISD::ANY_EXTEND)
+      Extract = Extract.getOperand(0);
     if (Extract.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
       return false;
 
@@ -12098,8 +12103,10 @@ SDValue PPCTargetLowering::DAGCombineBui
     return Reduced;
 
   // If we're building a vector out of extended elements from another vector
-  // we have P9 vector integer extend instructions.
-  if (Subtarget.hasP9Altivec()) {
+  // we have P9 vector integer extend instructions. The code assumes legal
+  // input types (i.e. it can't handle things like v4i16) so do not run before
+  // legalization.
+  if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) {
     Reduced = combineBVOfVecSExt(N, DAG);
     if (Reduced)
       return Reduced;

Copied: llvm/branches/release_70/test/CodeGen/PowerPC/pr38087.ll (from r339769, llvm/trunk/test/CodeGen/PowerPC/pr38087.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/CodeGen/PowerPC/pr38087.ll?p2=llvm/branches/release_70/test/CodeGen/PowerPC/pr38087.ll&p1=llvm/trunk/test/CodeGen/PowerPC/pr38087.ll&r1=339769&r2=339859&rev=339859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr38087.ll (original)
+++ llvm/branches/release_70/test/CodeGen/PowerPC/pr38087.ll Thu Aug 16 03:13:29 2018
@@ -11,8 +11,9 @@ declare { i32, i1 } @llvm.usub.with.over
 define void @draw_llvm_vs_variant0() {
 ; CHECK-LABEL: draw_llvm_vs_variant0:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lfd f0, 0(r3)
-; CHECK-NEXT:    xxpermdi v2, f0, f0, 2
+; CHECK-NEXT:    ldx r3, 0, r3
+; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    xxswapd v2, vs0
 ; CHECK-NEXT:    vmrglh v2, v2, v2
 ; CHECK-NEXT:    vextsh2w v2, v2
 ; CHECK-NEXT:    xvcvsxwsp vs0, v2